Cold-cathode driver and liquid crystal display

ABSTRACT

A cold cathode tube driving device using a piezoelectric transformer in which an output voltage varies depending on a frequency of an input voltage, as a booster transformer for driving a cold cathode tube, includes: a frequency dividing means which generates a driving pulse of an average frequency corresponding to frequency data outputted from a frequency setting means at a distribution cycle which is a driving pulse N cyclic period; a controller which controls a control cycle so as to perform the same driving for predetermined number of times A (A≧2) at the average frequency; and a burst pulse generating means which generates a pulse having a duty width in accordance with a dimming level externally applied thereto and having a frequency outputted from the controller. 
     A control cycle is A times (natural number) the distribution cycle and the driving is performed A times at the same average frequency, whereby a digital driving system using the frequency distribution of the driving pulse is achieved. Consequently, a space for the driving circuit can be saved and cost can be reduced. Further, a frequency distribution system is adopted, thereby obtaining frequency resolution required for satisfactory dimming performance and lighting performance. Moreover, a burst dimming system is adopted, thereby suppressing brightness flicker seen in a tube current control system. Additionally, there is no electric power loss seen in a system in which a power source is turned on or off and further a shield circuit is unnecessary because of a system in which the driving pulse is turned on or off. In particular, the control cycle is A times the distribution cycle and the burst dimming is performed in which the driving is executed A times at the same average frequency, whereby the brightness flicker can be prevented by controlling the tube current to be constant with high dimming resolution assured.

TECHNICAL FIELD

The present invention relates to a cold cathode tube driving devicewhich utilizes a piezoelectric transformer as a booster transformer fordriving a cold cathode tube, for example, a backlight of a liquidcrystal panel, and a liquid crystal display device on which the coldcathode tube driving device is mounted.

BACKGROUND ART

A piezoelectric transformer that can be reduced in size and thicknessand can bring high efficiency has been used, instead of anelectromagnetic transformer, as a booster transformer for driving a coldcathode tube that is a backlight of a liquid crystal panel. Thepiezoelectric transformer is generally a voltage converting element,which utilizes the piezoelectric effect of a piezoelectric element forgenerating mechanical oscillations and taking out from its secondaryelectrode side a voltage amplified depending on a voltage step-up ratiodetermined by the shape of the piezoelectric transformer.

FIG. 40 shows a general characteristic of a piezoelectric transformer.In the piezoelectric transformer, an output voltage at its secondaryside varies in accordance with a frequency of an AC voltage inputted toits primary side since the piezoelectric transformer has a resonancecharacteristic. Due to the aforementioned characteristic, the next formis popular as a method for controlling the brightness of the backlightat a constant level. Specifically, this method is such that thefrequency of the AC voltage for driving the piezoelectric transformer iscontrolled to obtain an amplitude of a desired level at the secondaryside, to thereby apply a stable voltage to the cold cathode tube. Alinear inclined portion in the frequency area higher than the resonancefrequency is utilized for the control.

FIG. 41 shows a general configuration of a backlight driving means. InFIG. 41, numeral 1 designates a piezoelectric transformer, 2 a coil, 3 aswitching transistor (FET (Field Effect Transistor)), 4 a cold cathodetube, 5 a current detector for detecting electric current flowingthrough the cold cathode tube 4 and 6 a driving pulse generating circuitthat compares the detected voltage by the current detector 5 with areference voltage for producing a driving pulse of a frequency accordingto its difference.

FIG. 42 shows waveforms at each means of the circuit shown in FIG. 41.In FIG. 42, a voltage A is an output voltage waveform (driving pulse) ofthe driving pulse generating circuit 6, a voltage B is an input voltagewaveform of the piezoelectric transformer 1 and a voltage C is an outputvoltage waveform of the piezoelectric transformer 1. The voltage C isgiven to the cold cathode tube 4 so that electric current (tube current)flows through the cold cathode tube 4. The current flowing through thecold cathode tube 4 is detected by the current detector 5. Although theinput voltage of the piezoelectric transformer 1 is desirably asinusoidal voltage, the following explanation is made with a half-wavesinusoidal voltage.

The coil 2 and the piezoelectric transformer 1 constitute a resonancecircuit. Its resonance frequency is determined by the inductance valueof the coil 2 and the input capacity value of the piezoelectrictransformer 1. Applying energy to the resonance circuit via the FET 3brings a half-wave sinusoidal voltage with the above-mentioned resonancefrequency (voltage B). Only the resonance frequency component possessedby the piezoelectric transformer 1 itself is drawn out from the outputof the piezoelectric transformer 1 to which the voltage B is inputted,with the result that the sinusoidal voltage that is the voltage C shownin FIG. 42 is outputted. This sinusoidal voltage C has the amplitudevarying in accordance with the frequency of the voltage B due to thecharacteristic shown in FIG. 40.

Utilizing this characteristic, the driving pulse generating circuit 6compares the voltage obtained from the current detector 5 with thereference voltage for controlling the frequency of the output voltagefrom the driving pulse generating circuit 6 such that the tube currentis made to be a desired value. Voltages A1 to C1 in FIG. 42 respectivelyshow waveforms of each means when the frequency of the driving pulse islowered. The lower the frequency becomes, the greater the amplitude ofthe sinusoidal voltage becomes.

As described above, a method for controlling the tube current by varyingthe frequency of the driving pulse is generally used for controlling thebrightness of the cold cathode tube 4 in the driving circuit of thepiezoelectric transformer 1.

Conventionally, a circuit for realizing the above-mentioned techniquehas generally been formed of an analog circuit. Accordingly, there is aproblem that the number of components is increased and the space for thecomponents is large. Particularly, it has been desired that the spacefor the driving circuit is saved since miniaturization of equipment isimportant in a portable imaging equipment such as a VTR integrated witha camera or a digital camera.

In view of this, an attempt has been made for saving a space for thedriving circuit and also reducing cost by digitizing the driving circuitto make one chip with the other LSIs (for example, liquid crystalcontroller or the like) (see Japanese Unexamined Patent Publication No.2000-133485 (document 1)).

Several 100 MHz to several GHz clocks are normally required in order toobtain practical dimming resolution with the driving of thepiezoelectric transformer of a digital system. The technique in thedocument 1 is a system in which a frequency of the driving pulse isdistributed. This system enables a dimming resolution by a frequencycontrol with approximately 10 MHz clocks.

The technique disclosed in the document 1 will briefly be explained. Inthe case of digitally producing a driving pulse, a frequency resolutionrequired for the dimming control cannot be obtained in a method forobtaining a driving pulse by simply dividing clocks. A sharpness Q ofthe resonance of the piezoelectric transformer is extremely great. Incase where the driving frequency of the piezoelectric transformer isabout 100 KHz, for example, the frequency resolution required for thedimming control is at intervals of several 10 Hz in the vicinity of 100KHz. However, in case where the clock frequency is 10 MHz and thedriving pulse of 100 KHz is produced by using this clock, for example,the frequency resolution of only about 1 KHz can be obtained in thevicinity of 100 KHz, so that it is difficult to realize not only dimmingperformance but also stable lighting.

In view of this, a configuration is made such that a frequency dividingratio is distributed in a predetermined driving cycle for obtaining aresolution with an average frequency as shown in FIG. 43. By thismethod, when the frequency dividing ratio is distributed in 100 cycles,for example, a hundred-fold frequency resolution can be obtained. Thismethod enables to incorporate a cold cathode tube driving device in adigital LSI, thereby being capable of reducing a space and cost.

The driving method disclosed in the document 1 is a system forperforming the dimming control by controlling the tube current. However,this method for performing the dimming control by controlling the tubecurrent has the following problems:

(1) The current flowing through the cold cathode tube is unstable in thearea where the tube current is small, so that the dimming level cannotbe greatly reduced.

(2) A luminous efficiency of the cold cathode tube varies depending upona current value, so that the luminous efficiency greatly changes inaccordance with the dimming level in the tube current control.

(3) In order to change the tube current, the driving frequency isrequired to be changed. However, the efficiency of the piezoelectrictransformer changes depending upon the driving frequency, so that thereis a limitation to obtain a high efficiency within a wide dimming range.

As a means for solving these problems, there has been known a technique(hereinafter referred to as a burst dimming) in which the driving isintermittently turned on and off at a frequency (for example, about 100Hz) that does not cause a brightness flicker. The dimming level ischanged by changing a duty ratio of turning-on and turning-off. Thistechnique has widely been used for not only a backlight driving circuitutilizing a piezoelectric transformer but also a backlight drivingcircuit utilizing a conventional electromagnetic transformer.

There are roughly the following two systems for realizing this burstdimming in the backlight driving circuit utilizing the piezoelectrictransformer. One of them is a method for turning on and turning off acircuit power source, while the other one is a method for turning on andturning off only the driving pulse with the circuit actuated.

The former method can be adopted to the conventional circuit. In thismethod, a starting control upon turning on a power source and a normalcontrol upon lighting are repeatedly executed. However, a shield circuitfor turning on and turning off the power source is required in a powersource line. An electric loss occurs due to this shield circuit, thusnot preferable in a portable equipment in particular.

On the other hand, the latter method requires a means for turning offthe detection of the tube current upon turning off the driving andholding the driving frequency at a predetermined value in addition tothe conventional circuit. In this case, there is no electric loss in thepower source line, thus excellent in the use of a portable equipment inparticular. A technique for realizing this method in an analog system isdisclosed, for example, in Japanese Unexamined Patent Publication No.11-298060 (1999) (document 2).

The technique disclosed in the document 2 will briefly be explained.FIG. 44 is a view simplifying the technique disclosed in the document 2.It is featured in that a voltage at the current detector 5 is held by asample holding means 8 upon turning off the driving, thereby holding theoscillation frequency of a voltage control oscillation circuit 12 at aconstant level and promptly starting the lighting upon restarting thedriving.

As described above, the burst dimming driving system can be realized byadding a simple circuit in the analog driving system. However, in casewhere the burst dimming is realized in the digital system by a frequencydistribution system, there arises the following subjects:

(1) The frequency distribution system is configured such that afrequency of a driving pulse is distributed in a predetermined cycle toobtain a frequency resolution with an average frequency. It performs acurrent control with the distribution cycle as one set. Therefore, incase where the ON/OFF duty ratio is optionally changed, a currentdetection that is correct on principle of the distribution system cannotbe executed, and hence, the current control is remarkably unstable.

(2) In case where the duty ratio is changed with a distribution cycleunit without destroying the distribution principle as shown in FIG. 45,a set of the distribution cycle is required in accordance with thedimming resolution in order to obtain a required dimming resolution. Bythis, the frequency of the burst cycle is remarkably reduced andbrightness flicker is increased. Additionally, when the burst periodrises high to a level that can suppress the brightness flicker, thedimming resolution cannot be obtained.

Further, there is a subject concerning a starting control upon the burstdimming (especially in case where the aimed brightness level is small)as a common subject of analog and digital systems. It is desirable tolight up with a desired brightness upon lighting. However, this has beendifficult in the conventional driving circuit because of the followingreasons.

There are following two methods for lighting with a desired brightness.The first one is a method for performing with the burst driving upon thestarting similar to the case upon the lighting as shown in FIG. 46. Thismethod does not require extra circuits since the burst control isadopted upon starting and lighting. Further, the brightness level isshifted to the aimed brightness level without sense of a incongruity,thereby being capable of obtaining a satisfactory lighting quality.

However, the lighting performance of the cold cathode tube isdeteriorated in this method, especially in case where the aimedbrightness level is low.

A cold cathode tube generally has reduced lighting performance at a lowtemperature or under a dark ambient illuminance. This problem has beenknown to be improved by rising the starting voltage or lengthening timefor applying the starting voltage.

However, the starting with the burst driving requires an extra time forapplying the starting voltage, thereby taking time to light.

Additionally, in order to prevent extra stress due to high pressurebeing placed on the piezoelectric transformer upon starting, aprotection function is provided to terminate the starting unlesslighting is executed even after a predetermined period. There may be thecase where lighting is not executed due to the influence of thisprotection function.

There is a method for rising the starting voltage upon the burstdriving. However, this causes further stress on the piezoelectrictransformer, thereby deteriorating reliability. Further, this methodrequires an extra circuit space to reinforce a measure for preventing adischarge caused by a high pressure, thus not preferable.

The second method is that, as shown in FIG. 47, continuous driving isperformed upon the starting in view of the lighting performance of thecold cathode tube, and then, the driving is promptly shifted to theburst driving after the lighting. This method requires a lightingdetecting means and a control switching means since the control isdifferent between upon the starting and upon the lighting. If an ideallighting detecting means can be obtained, it enables the lighting withthe aimed brightness level without deteriorating the lightingperformance of the cold cathode tube.

However, the conventional lighting detecting means is slow in detectingthe lighting, resulting in that the brightness is greatly changed by thetime of reaching the aimed brightness level as shown in FIG. 47, thatcauses a problem concerning the lighting quality.

The present invention is accomplished in view of the above-mentionedproblems, and an object thereof is to firstly propose a driving systemrealizing a burst dimming in a digital system, and to realize reducedcost and saved space in a cold cathode tube driving device that canperform a burst dimming.

Further, another object of the present invention is secondly to providea starting system excellent in lighting performance even in case wherethe aimed brightness level is low.

The other objects, features and advantages of the present invention willbe apparent from the following description.

DISCLOSURE OF THE INVENTION

[First Solving Means]

As a first means to solve the subjects, the present invention provides,as a booster transformer for driving a cold cathode tube that is a load,a cold cathode tube driving device using a piezoelectric transformer inwhich an output voltage varies in accordance with a frequency of aninput voltage, and including a data converting means, a smoothingprocess means, an error voltage calculating means, a frequency settingmeans, a frequency dividing means, a controller, a burst pulsegenerating means, an output enabling means and a power amplifying means.Each means may be achieved by hardware or software, or a hybridconfiguration in combination of hardware and software. The dataconverting means detects electric current flowing through the coldcathode tube and converts the detected current amount into digital data.The smoothing process means smoothes output data from the dataconverting means at a predetermined timing. The error voltagecalculating means compare smoothing data obtained from the smoothingprocess means with reference data for outputting error datacorresponding to its difference. The frequency setting means sets afrequency of a driving pulse for driving the piezoelectric transformerbased upon the error data applied from the error voltage calculatingmeans. An N cycle of the driving pulse is called “distribution cycle”.The frequency dividing means divides a clock of a predeterminedfrequency and generates a driving pulse of an average frequencycorresponding to the frequency data outputted from the frequency settingmeans in the distribution cycle. The controller controls a control cycleso as to perform the same driving A times (A is a natural number notless than 2) with the average frequency. The burst pulse generatingmeans generates a pulse having a duty width in accordance with a dimminglevel externally applied thereto and having a frequency outputted fromthe controller. The output enabling means turns on or off the output ofthe driving pulse outputted from the frequency dividing means inaccordance with the output value from the burst pulse generating means.The power amplifying means performs inversion with a switching by thedriving pulse from the output enabling means and then outputs to thepiezoelectric transformer. By the above-mentioned configuration, thedimming level is controlled for adjusting the brightness level of thecold cathode tube. It is to be noted that reference is made to FIG. 2 inan embodiment 1 described later concerning this configuration.

The operation of this configuration will be explained as follows. Thecontrol cycle is A times the distribution cycle (N cycle of the drivingpulse) so that driving is performed A times at the same averagefrequency. Specifically, the width of the active period of the burstpulse is set not shorter than the distribution cycle.

The frequency dividing means repeatedly performs the driving A times atthe distribution cycle having the average frequency by the combinationof the frequency dividing ratio over the control cycle, to therebyobtain a frequency resolution with high accuracy. Corresponding to this,it is a principle that the current flowing through the cold cathode tubethat is a load is detected per the distribution cycle unit. However, ifthe burst driving control is executed in one distribution cycle unit soas to obtain constant tube current, the burst pulse width (ON-period)becomes shorter than the distribution cycle, resulting in that thecurrent at ON-time cannot be controlled to be constant. Therefore, thedriving is performed in plural cycles (distribution cycle plural cycles)at the same average frequency so that the burst pulse width (ON-time) isnot shorter than one distribution cycle and the sampling number of thecurrent detection is equal to the sampling number in the distributioncycle. This configuration assures a period of time for detecting averagecurrent during one distribution cycle. As a result, a control can besatisfactorily performed wherein the tube current is constant.

In other words, the control cycle is A times (natural number) thedistribution cycle and the driving is performed A times at the sameaverage frequency, whereby a satisfactory burst dimming can be realizedeven in a digital driving system using the frequency distribution of thedriving pulse. Specific explanation is as follows. The space for thedriving circuit can be saved and cost can be reduced because of thedigital driving system. Further, frequency resolution required forsatisfactory dimming performance and lighting performance can beobtained because of the frequency distribution system. Moreover,brightness flicker seen in a tube current control system can besuppressed because of the burst dimming system. Additionally, there isno electric power loss seen in a system in which a power source isturned on or off and further a shield circuit is unnecessary because ofa system in which the driving pulse is turned on or off. As describedabove, the control cycle is A times the distribution cycle and the burstdimming is performed in which the driving is executed A times at thesame average frequency, in particular, whereby the brightness flickercan be prevented by controlling the tube current to be constant withhigh dimming resolution assured.

A preferable mode in the first means to solve the subjects is that thesmoothing process means is configured such that an acquisition range ofdata to be smoothed is variable in a unit of multiple of thedistribution cycle. Reference is made to FIGS. 7 and 8 in the embodiment1 described later concerning this operation. More specifically, adetection width adjusting means is provided for calculating the dataacquisition range based upon the burst pulse from the burst pulsegenerating means and the control timing pule from the controller. Byadjusting the data acquisition range in accordance with the burst pulsewidth, the greater the dimming level becomes, the more the currentdetection accuracy enhances.

A preferable mode in the above is that the smoothing process means isconfigured to perform an averaging process (as an averaging means). Theaveraging means is preferably used for detecting with high accuracycurrent flowing through the cold cathode tube that is a load. It is tobe noted that it may be replaced with normal filter means so long as astrict brightness precision is especially not required.

In the first means to solve the subjects, the controlling process meanscomprising the smoothing process means, error voltage calculating means,frequency setting means, frequency dividing means, controller, burstpulse generating means and output enabling means may be achieved by ahardware or a software or a hybrid configuration in combination of thehardware and software. Reference is made to FIG. 20 in the embodiment 1described later concerning the case where the controlling process meansis achieved by a software.

A liquid crystal display device mounted thereto the cold cathode tubedriving device having the above-mentioned configuration solves theabove-mentioned subjects. The liquid crystal display device includes aliquid crystal panel, a cold cathode tube that is a backlight of theliquid crystal panel and the cold cathode tube driving device having theabove-mentioned configuration, wherein the piezoelectric transformer inthe cold cathode tube driving device is connected to the cold cathodetube. The driving pulse from the output enabling means in the coldcathode tube driving device having the above-mentioned configuration issupplied to a switching element in the power amplifying means to drivethe piezoelectric transformer, to thereby control the dimming level foradjusting the brightness level of an image displayed on the liquidcrystal panel.

According to the present invention, the burst dimming can be realized bydriving the piezoelectric transformer with a digital driving systemusing the frequency distribution of the driving pulse in the liquidcrystal display device in which the cold cathode tube that is thebacklight of the liquid crystal panel is driven by the piezoelectrictransformer. Specifically, the frequency resolution required for thenecessary dimming can be obtained, whereby the current flowing thoughthe cold cathode tube is stable even in an area where the tube currentis relatively small, and hence the dimming level can be made low. As thesecondary effect of the digital driving system, reduced cost and savedspace can be obtained by the formation of one chip with other LSIs, thatcontributes to miniaturization of small-sized imaging equipment.

[Second Solving Means]

As a second means to solve the subjects, the present invention provides,as a booster transformer for driving a cold cathode tube that is a load,a cold cathode tube driving device using a piezoelectric transformer inwhich an output voltage varies in accordance with a frequency of aninput voltage, and including a data converting means, a smoothingprocess means, an error voltage calculating means, a frequency settingmeans, a frequency dividing means, a controller, a burst pulsegenerating means, an output enabling means and a power amplifying means,those means being configured by the same manner as those in the firstmeans, wherein the controller controls the control cycle such that thesame driving is performed predetermined A×k times (A≧2, k is a variablevalue in accordance with the distribution cycle) at the averagefrequency, and further a distribution number adjusting means having thefollowing function is newly added as a component element. Specifically,the distribution number adjusting means sets the values of N and k thatdetermine the distribution cycle in synchronization with the burst pulsewidth outputted from the burst pulse generating means. By theabove-mentioned configuration, the dimming level is controlled to adjustthe brightness level of the cold cathode tube.

Compared to the first means, the feature of the second means is that theconfiguration of the controller is different from that of the firstmeans and the distribution number adjusting means is added. Thedistribution number adjusting means may be achieved by a hardware orsoftware, or may be achieved by a hybrid configuration of a software anda hardware. The controller in the first means controls the control cyclesuch that the driving is repeatedly performed given predetermined timesA (A≧2) at the same average frequency. On the other hand, the controllerin the second means controls the control cycle such that the driving isrepeatedly performed given predetermined times A×k at the same averagefrequency, wherein k is a variable value according to the distributioncycle. Additionally, the distribution number adjusting means is newlyadded to set the values of N and k that determine the distribution cyclein synchronization with the burst pulse width. Reference is made to FIG.9 in an embodiment 2 described later concerning the configuration of thesecond means. Further, reference is made to FIG. 10 concerning that thevalue k is variable.

A preferable mode in the second means is that the distribution numberadjusting means determines the value of k such that the control cycle bythe controller is made constant irrespective of the value N (thatdetermines the distribution cycle).

Further, a preferable mode in the second means is that the value A ofthe controller is adjusted in synchronization with the duty of the burstpulse outputted from the burst pulse generating means.

The operation by the above-mentioned configuration is as follows. Inorder to correctly detect the average current flowing through the coldcathode tube that is a load, a detection range of a minimum of onedistribution cycle is required. In the first means, the burst pulsewidth is required to be made greater than the distribution cycle width,so that there is a restriction in the lower limit of the dimming level.The second means is accomplished in view of this. Specifically, althoughthe distribution number N (distribution cycle) is changed in accordancewith the burst pulse width, the number of times for driving at the sameaverage frequency is simultaneously changed so as not to change thecontrol cycle (i.e., cycle of the burst pulse) even if the distributioncycle is changed. Briefly, N×k is made constant.

For assuring the detection during one distribution cycle, the duty ofthe burst pulse becomes great when the distribution number is so many,while the small duty is enough when the distribution number is small. Onthe other hand, the current accuracy is high as the distribution numberis great. However, the dimming level of about 50 to 100% used for theimage appreciation normally requires the dimming precision. A lowbrightness means does not require the dimming precision compared to ahigh brightness means. A low brightness mode is used to reduce powerconsumption when only a stand-by mode or OSD (on-screen display) isdisplayed. In the case of the low brightness (in case where the burstpulse width is not more than the predetermined value), the distributionnumber is made small and the number of times for driving at the samefrequency increases so as not to change the burst frequency (see FIG.10). Hence, changing the distribution number in accordance with theburst pulse width enables to lower the dimming level, thereby beingcapable of enlarging the dimming range.

A preferable mode in the first means to solve the subjects is that thesmoothing process means is configured such that an acquisition range ofdata to be smoothed is variable in a unit of multiple of thedistribution cycle. More specifically, a detection width adjusting meansis provided for calculating the data acquisition range based upon theburst pulse from the burst pulse generating means and the control timingpule from the controller (see FIGS. 7 and 8). By adjusting the dataacquisition range in accordance with the burst pulse width, the greaterthe dimming level becomes, the more the current detection accuracyenhances.

A preferable mode in the above is that the smoothing process means isconfigured to perform an averaging process (as an averaging means). Theaveraging means is preferably used for detecting with high accuracycurrent flowing through the cold cathode tube that is a load. It is tobe noted that it may be replaced with normal filter means so long as astrict brightness precision is especially not required.

In the second means to solve the subjects, the controlling process meanscomprising the smoothing process means, error voltage calculating means,frequency setting means, frequency dividing means, controller, burstpulse generating means and output enabling means may be achieved by ahardware or a software or a hybrid configuration in combination of thehardware and software.

A liquid crystal display device mounted thereto the cold cathode tubedriving device having the above-mentioned configuration includes aliquid crystal panel, a cold cathode tube that is a backlight of theliquid crystal panel and the cold cathode tube driving device having theabove-mentioned configuration, wherein the piezoelectric transformer inthe cold cathode tube driving device is connected to the cold cathodetube. The driving pulse from the output enabling means in the coldcathode tube driving device having the above-mentioned configuration issupplied to a switching element in the power amplifying means to drivethe piezoelectric transformer, to thereby control the dimming level foradjusting the brightness level of an image displayed on the liquidcrystal panel.

According to the present invention, the burst dimming can be realized,like the first means to solve the subjects, by driving the piezoelectrictransformer with a digital driving system using the frequencydistribution of the driving pulse in the liquid crystal display devicein which the cold cathode tube that is the backlight of the liquidcrystal panel is driven by the piezoelectric transformer. Specifically,the frequency resolution required for the necessary dimming can beobtained, whereby the current flowing though the cold cathode tube isstable even in an area where the tube current is relatively small, andhence the dimming level can be made low. Additionally, changing thedistribution number according to the burst pulse width enables tofurther lower the dimming level, thereby being capable of enlarging thedimming range.

[Third Solving Means]

As a third means to solve the subjects, the present invention provides,as a booster transformer for driving a cold cathode tube that is a load,a cold cathode tube driving device using a piezoelectric transformer inwhich an output voltage varies in accordance with a frequency of aninput voltage, and including a data converting means, a smoothingprocess means, an error voltage calculating means, a frequency settingmeans, a frequency dividing means, a controller, a burst pulsegenerating means, an output enabling means and a power amplifying means,those means being configured by the same manner as those in the firstmeans, wherein the data converting means detects current flowing throughthe cold cathode tube and an input voltage of the cold cathode tube andconverts the respective current values into digital data. The coldcathode tube driving device further includes, as new structural element,a lighting detecting means, a control cycle switching means and adimming level switching means, those having the following functions.Each means may be achieved by a software or a hardware, or a hybridconfiguration in combination with a software and hardware.

The lighting detecting means detects lighting from the output from thedata converting means and applies a lighting detection pulse that is thedetected result to the control cycle switching means and dimming levelswitching means. The control cycle switching means changes over thenumber of times A in synchronization with the lighting detection pulseoutputted from the lighting detecting means and applies the same to thefrequency setting means. The dimming level switching means performs thechange-over between the externally applied dimming level and theseparately set dimming level in synchronization with the lightingdetection pulse outputted from the lighting detecting means, and appliesthe resultant level to the burst pulse generating means. By thisconfiguration, the dimming level is controlled for adjusting thebrightness level of the cold cathode tube.

The features of the third means to solve the subjects compared to thefirst means are that the configuration of the data converting means isdifferent and the lighting detecting means, control cycle switchingmeans and dimming level switching means are newly added. The dataconverting means has a function of detecting the input voltage of thecold cathode tube in addition to the function of detecting the currentflowing through the cold cathode tube. Moreover, added in the thirdmeans are the lighting detecting means for detecting the lighting fromthe output from the data converting means, control cycle switching meansfor changing the number of times A in synchronization with the lightingdetection pulse outputted from the lighting detecting means and dimminglevel switching means for performing the change-over between theexternally applied dimming level and the separately set dimming level insynchronization with the lighting detection pulse. The controllercontrols the control cycle such that the same driving is executedpredetermined number of times A (A is a natural integer not less than 2)at the same frequency like the first means to solve the subjects.Reference is made to FIG. 13 in an embodiment 3 described laterconcerning the configuration of the third means. (The smoothing processmeans is illustrated as the averaging means as its one example.)

A preferable mode in the third means is that the number of times Ashowing the control cycle set at the control cycle switching means isset such that the number of times A at the starting is smaller than thenumber of times A at the lighting.

Moreover, a preferable mode in the third means is that the distributionnumber at the frequency dividing means is changed over insynchronization with the lighting detection pulse outputted from thelighting detecting means, and the distribution cycle at the starting isset smaller than the distribution cycle at the full lighting.

Further, a preferable mode in the third means is that the dimming levelswitching means outputs a dimming level representing 100% continuousdriving when the lighting detection pulse outputted from the lightingdetecting means is a value showing the non-lighting state.

The operation of the above configuration is as follows. The dimminglevel and the burst pulse width are correlated with each other. When theburst pulse is effective, the piezoelectric transformer is driven toapply a voltage to the cold cathode tube. If the dimming level is lowand the burst pulse width is narrow, the lighting performance at thestarting is unsatisfactory. The third means is accomplished in view ofthis. The burst pulse width is set somewhat great so as to achieve asomewhat high dimming level at the dimming level switching means by thetime when the lighting of the cold cathode tube is realized. Forexample, the dimming level is set to 100% to achieve a continuousdriving. This operation can assure a long time taken to apply a voltageto the cold cathode tube from the piezoelectric transformer. Further,the control cycle is set rather short at the control cycle switchingmeans, whereby the lighting is detected within the burst pulse width atthe MIN dimming. Consequently, the variation in the brightnessimmediately after the lighting is suppressed. When the tube currentflows through the cold cathode tube by the completion of the lighting,the lighting detecting means detects the lighting and controls thecontrol cycle switching means and dimming level switching means. Thedimming level is promptly shifted to a desired dimming level after thedetection of the lighting. By the multiplier effect described above, thelighting performance is satisfactory even if the dimming level is low.

By controlling the distribution number adjusting means based upon thelighting detection pulse from the lighting detecting means to make thedistribution number at the starting smaller than the distribution numberat the full lighting, an irregular period is made short that is abrightness change at the lighting, to thereby improve a lighting qualityand obtain a satisfactory lighting performance.

In the third means to solve the subjects, the controlling process meanscomprising the smoothing process means, error voltage calculating means,frequency setting means, frequency dividing means, controller, controlcycle switching means, dimming level switching means, burst pulsegenerating means and output enabling means may be achieved by a hardwareor a software or a hybrid configuration in combination of the hardwareand software.

A liquid crystal display device mounted thereto the cold cathode tubedriving device having the above-mentioned configuration includes aliquid crystal panel, a cold cathode tube that is a backlight of theliquid crystal panel and the cold cathode tube driving device having theabove-mentioned configuration, wherein the piezoelectric transformer inthe cold cathode tube driving device is connected to the cold cathodetube. According to the liquid crystal display device, the lightingperformance is satisfactory even if the dimming level of the coldcathode tube that is the backlight of the liquid crystal panel is low.

Required to the piezoelectric transformer for driving the cold cathodetube that is the backlight basically are dimming function, low electricpower (high power conversion efficiency) or the like. Further, itssource is battery in case where it is used in portable equipment such asa notebook-sized personal computer or a digital video camera. However, astable source cannot be obtained by the battery source. Accordingly,stable lighting and stable power conversion efficiency within a widepower voltage range are desired considering by paying attention to thebattery source.

As a countermeasure, there has conventionally been proposed a method forchanging a duty ratio of the driving in accordance with the power supplyvoltage in an analog driving system. However, in case where this methodis performed in a digital driving system, the resolution of the dutyratio is rough when the clock frequency is low, thereby not obtaining asatisfactory performance. Raising the clock frequency can assure theresolution, but it causes increased circuit power or increased radiatedinterference, thus unpractical. Therefore, it is desired that the dutyratio of the driving pulse can be adjusted in intervals of as small aspossible for obtaining a satisfactory performance within a wide powersupply voltage range.

Fourth means and the following means to solve the subjects of theinvention described later are accomplished in view of theabove-mentioned subject, and propose a duty control system in a digitaldriving system without deteriorating an efficiency for aiming to realizea cold cathode tube driving device coping with a power supply voltage ofa wide range.

The present invention concerning a cold cathode tube driving device inwhich a power supply voltage variation is considered solves theabove-mentioned subject by taking the following measures.

[Fourth Solving Means]

The present invention of the fourth means to solve the subjects providesa cold cathode tube driving device that generates a driving pulseobtained by dividing a clock of a predetermined frequency in accordancewith a frequency dividing ratio corresponding to a difference between anelectric amount in a cold cathode tube that is a load of a piezoelectrictransformer and a reference electric amount, and then outputs thegenerated pulse to the piezoelectric transformer, this device includinga frequency setting means, a frequency dividing means, a power supplyvoltage detecting means, a pulse width calculating means and a pulsewidth adjusting means, each of those means having the followingfunctions. Each means may be achieved by a hardware or a software, or ahybrid configuration in combination of a hardware and a software.

The frequency setting means obtains dividing ratio information as to thedriving pulse from the information of the difference, and then appliesthe obtained information to the frequency dividing means and pulse widthcalculating means. The frequency dividing means produces a distributionpulse (a driving pulse for distributing a frequency dividing ratio) thatis a pulse for distributing a frequency dividing ratio based upon thedividing ratio information from the frequency setting means. The powersupply voltage detecting means detects a power supply voltage andapplies the information of the power supply voltage to the pulse widthcalculating means. The pulse width calculating means calculatesinformation of the pulse width of the distribution pulse based upon thepower supply voltage information from the power supply voltage detectingmeans and the dividing ratio information from the frequency settingmeans and applies the calculated information to the pulse widthadjusting means. The pulse width adjusting means produces an extendedpulse having a pulse width obtained by extending the pulse width of thedistribution pulse based upon the pulse width information from the pulsewidth calculating means as well as performs a change-over between thedistribution pulse and the extended pulse based upon the pulse widthinformation and then outputs the resultant to a driving element of thepiezoelectric transformer. Reference is made to FIG. 21 in an embodiment4 described later concerning this configuration.

The operation of this configuration is as follows. The pulse widthcalculating means applies the pulse width information according to thedetected power supply voltage to the pulse width adjusting means. Thepulse width increases in principle as the power supply voltage lowers(see FIG. 24). The pulse width adjusting means produces the extendedpulse from the distribution pulse, as well as selects either one of thedistribution pulse and the extended pulse based upon the pulse widthinformation, i.e., the detected power supply voltage, and then outputsthe selected one to the driving element of the piezoelectrictransformer.

The production of the extended pulse from the distribution pulse isdigitally executed. A pulse obtained by shifting the timing of thedistribution pulse is produced. The pulse having the shifted timing iscomposed with the initial distribution pulse by taking a logical sum,resulting in producing the extended pulse having a width greater thanthat of the distribution pulse. The extended pulse has a pulse widthextended by a period of the shifted timing. How much to shift the timingis determined based upon the pulse width information corresponding tothe detected power supply voltage. Further, which one is selected fromthe initial distribution pulse and the extended pulse is also determinedbased upon the pulse width information. By this process, the drivingpulse having a pulse width corresponding to the detected power supplyvoltage can digitally be realized to be produced. The period of shift isset as smaller as possible.

This configuration can provide a driving pulse having an optimum pulsewidth in a wide power supply voltage range even in a digital drivingsystem. The resolution of the pulse width can be made twice that of thedistribution pulse. This leads to reduce a power consumption due to animprovement in efficiency and to prevent a break-down of an FET orpiezoelectric transformer because of a surge upon driving thepiezoelectric transformer, thereby bringing a great effect.

There are a method by latching at a leading edge of a clock, a methodusing a delay element and a method of combining these methods in orderto produce a pulse having a timing shifted from the distribution pulse.

Examples of a preferable mode in the fourth means are as follows. Thepulse width calculating means is configured to output the pulse widthinformation obtained from the power supply voltage information from thepower supply voltage detecting means and the dividing ratio informationfrom the frequency setting means as data including decimal meanscorresponding to one cycle or less of a clock. Further, the pulse widthadjusting means is configured to include a pulse width shaping means, apulse width extending means and a switching means. Specifically, thepulse width shaping means shapes the pulse width of the distributionpulse outputted from the frequency dividing means into a valuecorresponding to an integer means of the pulse width information. Thepulse width extending means converts the output from the pulse widthshaping means into the extended pulse having an extended pulse width.One or more pulse width extending means are provided. The switchingmeans performs a change-over between the output from the pulse widthextending means and the output from the pulse width shaping means inaccordance with the value of the decimal means of the pulse widthinformation and outputs the resultant. Reference is made to FIGS. 25 to27 in the embodiment 4 described later concerning this configuration.

The operation by this configuration is as follows. The distributionnumber is defined by the number of the initial distribution pulsesexisting in one distribution cycle. This distribution number is anatural number. When the pulse width is adjusted only by adjusting thedistribution number, all the adjustment that can be made is only by thenatural number unit. Specifically, the pulse width next greater than thedistribution number N is (N+1), while the pulse width next smaller thanthe distribution pulse is (N−1). On the other hand, the present measureis to adjust the pulse width at a level of the tenth's place, not by thenatural number unit.

The present invention having the above-mentioned configuration can bedescribed as follows by illustrating from another angle of view. Thepresent invention of the fourth means to solve the subjects provides acold cathode tube driving device that generates a driving pulse obtainedby dividing a clock of a predetermined frequency in accordance with afrequency dividing ratio corresponding to a difference between anelectric amount in a cold cathode tube that is a load of a piezoelectrictransformer and a reference electric amount, and then outputs thegenerated pulse to the piezoelectric transformer, this device includinga frequency setting means, a frequency dividing means, a power supplyvoltage detecting means, a pulse width calculating means, a pulse widthshaping means, a pulse width extending means and a switching means, eachof those means having the following functions. The frequency settingmeans obtains dividing ratio information as to the driving pulse fromthe information of the difference. The frequency dividing means producesa distribution pulse having a dividing ratio of D+1 L times (L>K) duringK cycles of the driving pulse with respect to the reference dividingratio D. The power supply voltage detecting means detects an inputtedpower supply voltage. The pulse width calculating means outputs thepulse width information obtained from the power supply voltageinformation from the power supply voltage detecting means and thedividing ratio information from the frequency setting means as dataincluding decimal means corresponding to one cycle or less of a clock.The pulse width shaping means shapes the pulse width of the distributionpulse outputted from the frequency dividing means into a valuecorresponding to an integer means of the pulse width information. Thepulse width extending means converts the output from the pulse widthshaping means into the extended pulse having an extended pulse width.One or more pulse width extending means are provided. The switchingmeans performs a change-over between the output from the pulse widthextending means and the output from the pulse width shaping means inaccordance with the value of the decimal means of the pulse widthinformation and outputs the resultant to a driving element of thepiezoelectric transformer. Reference is made to FIG. 28 in theembodiment 4 described later concerning this configuration.

A preferable mode in the above-mentioned configuration is that the pulsewidth extending means includes a delay fine-adjusting means thatconverts the output from the pulse width shaping means into an extendedpulse having a pulse width extended with the respective delay differenceset shorter than one cycle of the clock.

Further, a preferable mode in the above configuration is that the delayfine-adjusting means is configured by a flip-flop that latches at atrailing edge of a clock. In this case, a pulse width resolution with adouble precision by using a trailing edge of a clock can be obtainedwithout deviating from a designing technique of a digital LSI.

[Fifth Solving Means]

A fifth means to solve the subjects solves the above-mentioned subjectby taking the following measures in a cold cathode tube driving devicein which a power supply voltage variation is considered.

The present invention of the fifth means to solve the subjects providesa cold cathode tube driving device that generates a driving pulseobtained by dividing a clock of a predetermined frequency in accordancewith a frequency dividing ratio corresponding to a difference between anelectric amount in a cold cathode tube that is a load of a piezoelectrictransformer and a reference electric amount, and then outputs thegenerated pulse to the piezoelectric transformer, this device includinga frequency setting means, a frequency dividing means, a power supplyvoltage detecting means, a pulse width calculating means and a pulsewidth adjusting means, each of those means having the followingfunctions. Each means may be achieved by a hardware or a software, or ahybrid configuration in combination of a hardware and a software.

The frequency setting means obtains dividing ratio information as to thedriving pulse from the information of the difference, and then appliesthe obtained information to the frequency dividing means and pulse widthcalculating means. The frequency dividing means produces a distributionpulse (a driving pulse for distributing a frequency dividing ratio) thatis a pulse for distributing a frequency dividing ratio based upon thedividing ratio information from the frequency setting means, and appliesthe produced pulse to the pulse width adjusting means. The power supplyvoltage detecting means detects a power supply voltage and applies theinformation of the power supply voltage to the pulse width calculatingmeans. The pulse width calculating means calculates information of thepulse width of the distribution pulse based upon the power supplyvoltage information from the power supply voltage detecting means andthe dividing ratio information from the frequency setting means andapplies the calculated information to the pulse width adjusting means.The pulse width adjusting means produces an extended pulse having apulse width obtained by extending the pulse width of the distributionpulse by 0.5 cycles, produces a delayed pulse and delayed and extendedpulse each having a pulse width obtained by respectively delaying thedistribution pulse and extended pulse by 0.5 cycles based upon the pulsewidth information from the pulse width calculating means, performs achange-over among the distribution pulse, extended pulse, delayed pulseand delayed and extended pulse based upon the pulse width information,and then, outputs the resultant to a driving element of thepiezoelectric transformer. Reference is made to FIG. 30 in an embodiment5 described later concerning this configuration.

The difference from the fourth means lies in the pulse width adjustingmeans. The pulse width adjusting means in the fifth means producespulses of three types from the distribution pulse and selects one pulseamong pulses of four types in total. Four types are (1) distributionpulse, (2) extended pulse having a pulse width obtained by extending thepulse width of the distribution pulse, (3) delayed pulse obtained bydelaying the distribution pulse and (4) delayed and extended pulseobtained by delaying the extended pulse.

By this configuration, even in case where high precision has alreadybeen aimed in the frequency dividing ratio of the driving pulse by usingthe trailing edge of a clock, the cold cathode tube driving device ofthis embodiment can finely adjust the pulse width of the driving pulseby effectively using the trailing edge of a clock without hindering theeffect of this case, to thereby obtain an optimum pulse width inaccordance with a power supply voltage. A double resolution, i.e., aresolution having precision four times that of the distribution pulse intotal can be obtained compared to the fourth means, whereby a pulsewidth control with higher precision can be obtained (see FIG. 31). Aneffect in power consumption and effect for preventing a break-down dueto a surge because of the other improvements in efficiency can similarlybe obtained.

Examples of a preferable mode in the fifth means are as follows. Thepulse width calculating means is configured to output the pulse widthinformation obtained from the power supply voltage information from thepower supply voltage detecting means and the dividing ratio informationfrom the frequency setting means as data including decimal meanscorresponding to one cycle or less of a clock. Further, the pulse widthadjusting means is configured to include a pulse width shaping means, a1-clock-cycle delaying means, a 0.5-clock-cycle delaying means and aswitching means. Specifically, the pulse width shaping means shapes thepulse width of the distribution pulse outputted from the frequencydividing means into a value corresponding to an integer means of thepulse width information. The 1-clock-cycle delaying means latches theoutput from the pulse width shaping means at the leading edge of aclock. The 0.5-clock-cycle delaying means latches the output from thepulse width shaping means at the trailing edge of a clock for producinga delay pulse. An extended pulse is formed by taking a logical sum(first logical sum) of the delay pulse that is the output from the0.5-clock-cycle delaying means and the distribution pulse that is theoutput from the pulse width adjusting means, while a delayed andextended pulse is formed by taking a logical sum (second logical sum) ofthe delay pulse that is the output from the 0.5-clock-cycle delayingmeans and the extended pulse that is the output from the 1-clock-cycledelaying means.

The switching means outputs each pulse obtained in the following fourpatterns as a driving pulse to the driving element of the piezoelectrictransformer.

(1) When low-order 1-bit value of the A-bit pulse width information isat low level and the dividing ratio is D, it outputs the distributionpulse that is the output from the pulse width shaping means.

(2) When low-order 1-bit value of the A-bit pulse width information isat low level and the dividing ratio is D+1, it outputs the delayed pulsethat is the output from the 0.5-clock-cycle delaying means.

(3) When low-order 1-bit value of the A-bit pulse width information isat high level and the dividing ratio is D, it outputs the extended pulsethat is the first logical sum.

(4) When low-order 1-bit value of the A-bit pulse width information isat high level and the dividing ratio is D+1, it outputs the delayed andextended pulse that is the second logical sum.

Reference is made to FIGS. 30 and 31 in the embodiment 5 described laterconcerning this configuration.

The present invention having the above-mentioned configuration can bedescribed as follows by illustrating from another angle of view. Thepresent invention of the fifth means to solve the subjects provides acold cathode tube driving device that generates a driving pulse obtainedby dividing a clock of a predetermined frequency in accordance with afrequency dividing ratio corresponding to a difference between anelectric amount in a cold cathode tube that is a load of a piezoelectrictransformer and a reference electric amount, and then outputs thegenerated pulse to the piezoelectric transformer, this device includinga frequency setting means, a frequency dividing means, a power supplyvoltage detecting means, a pulse width calculating means, a pulse widthshaping means, a 1-clock-cycle delaying means, a 0.5-clock-cycledelaying means, a pulse width extending means and a switching means,each of those means having the following functions. The frequencysetting means obtains dividing ratio information as to the driving pulsefrom the information of the difference. The frequency dividing meansproduces a distribution pulse having a dividing ratio of D+1 L times(L<K) during K cycles of the driving pulse with respect to the referencedividing ratio D. The power supply voltage detecting means detects aninputted power supply voltage. The pulse width calculating means outputsthe pulse width information obtained from the power supply voltageinformation from the power supply voltage detecting means and thedividing ratio information from the frequency setting means as dataincluding decimal means corresponding to one cycle or less of a clock.The pulse width shaping means shapes the pulse width of the distributionpulse outputted from the frequency dividing means into a valuecorresponding to an integer means of the pulse width information. The1-clock-cycle delaying means latches the output from the pulse widthshaping means at the leading edge of a clock. The 0.5-clock-cycledelaying means latches the output from the pulse width shaping means atthe trailing edge of a clock. The switching means is configured to havethe following functions.

(1) When low-order 1-bit value of the A-bit pulse width information isat low level and the dividing ratio is D, it outputs the output from thepulse width shaping means to the driving element of the piezoelectrictransformer.

(2) When low-order 1-bit value of the A-bit pulse width information isat low level and the dividing ratio is D+1, it outputs the output fromthe 0.5-clock-cycle delaying means to the driving element.

(3) When low-order 1-bit value of the A-bit pulse width information isat high level and the dividing ratio is D, it outputs the logical sum ofthe output from the 0.5-clock-cycle delaying means and the output fromthe pulse width adjusting means to the driving element.

(4) When low-order 1-bit value of the A-bit pulse width information isat high level and the dividing ratio is D+1, it outputs the logical sumof the output from the 0.5-clock-cycle delaying means and the outputfrom the 1-clock-cycle delaying means to the driving element.

The switching means is configured as described above.

[Sixth Solving Means]

Sixth means to solve the subjects solves the above-mentioned subject bytaking the following measures in a cold cathode tube driving device inwhich a power supply voltage variation is considered.

The present invention of the sixth means to solve the subjects providesa cold cathode tube driving device that generates a driving pulseobtained by dividing a clock of a predetermined frequency in accordancewith a frequency dividing ratio corresponding to a difference between anelectric amount in a cold cathode tube that is a load of a piezoelectrictransformer and a reference electric amount, and then outputs thegenerated pulse to the piezoelectric transformer, this device includinga frequency setting means, a frequency dividing means, a power supplyvoltage detecting means, a pulse width calculating means, a pulse widthdistributing means and a pulse width adjusting means, each of thosemeans having the following functions. Each means may be achieved by ahardware or a software, or a hybrid configuration in combination of ahardware and a software.

The frequency setting means obtains dividing ratio information as to thedriving pulse from the information of the difference, and then appliesthe obtained information to the frequency dividing means and pulse widthcalculating means. The frequency dividing means produces a distributionpulse (a driving pulse for distributing a frequency dividing ratio) thatis a pulse for distributing a frequency dividing ratio based upon thedividing ratio information from the frequency setting means, and appliesthe produced pulse to the pulse width adjusting means. The power supplyvoltage detecting means detects a power supply voltage and applies theinformation of the power supply voltage to the pulse width calculatingmeans. The pulse width calculating means calculates information of thepulse width of the distribution pulse based upon the power supplyvoltage information from the power supply voltage detecting means andthe dividing ratio information from the frequency setting means andapplies the calculated information to the pulse width distributingmeans. The pulse width distributing means inputs the pulse widthinformation from the pulse width calculating means, increases the pulsewidth information at a predetermined timing and then outputs theresultant to the pulse width calculating means. The pulse widthadjusting means adjusts the pulse width of the distribution pulse fromthe frequency dividing means according to the output from the pulsewidth distributing means and outputs the resultant to the drivingelement of the piezoelectric transformer. Reference is made to FIG. 33in an embodiment 6 described later concerning this configuration.

The sixth means provides a system in which the pulse width isdistributed at a predetermined cycle for obtaining a resolution of apulse duty at an average pulse width in a driving pulse during apredetermined cycle, to thereby be capable of obtaining a pulse widthadjustment with highly enhanced resolution compared to the fourth meansand fifth means described above. This system enables to perform a smoothduty control with respect to a power supply voltage, thereby improving adriving efficiency of the piezoelectric transformer. This greatlycontributes to power reduction at a backlight means. Further, thissystem can be used in synchronization with the distribution in thefrequency dividing ratio, thereby not ruining the conventional effect.Additionally, it can be used with the above-mentioned fourth means andfifth means. The combination of these systems is very effective forimproving efficiency.

A preferable mode in the sixth means to solve the subjects is that thepulse width calculating means is configured to output the pulse widthinformation as A-bit data based upon the power supply voltageinformation and the dividing ratio information obtained at the frequencydividing means, and that the pulse width distributing means isconfigured to output data obtained by adding 1 to the high-order(A-n)-bit data of the A-bit pulse width information during nth root of 2of the distribution pulse the times represented by the low-order n-bitof the A-bit pulse width information.

The present invention of the sixth means having the above-mentionedconfiguration can be described as follows by illustrating from anotherangle of view. The present invention of the sixth means to solve thesubjects provides a cold cathode tube driving device that generates adriving pulse obtained by dividing a clock of a predetermined frequencyin accordance with a frequency dividing ratio corresponding to adifference between an electric amount in a cold cathode tube that is aload of a piezoelectric transformer and a reference electric amount, andthen outputs the generated pulse to the piezoelectric transformer, thisdevice including a frequency setting means for obtaining dividing ratioinformation as to the driving pulse from the information of thedifference, a frequency dividing means that produces a distributionpulse having a dividing ratio of D+1 L times (L<K) during K cycles ofthe driving pulse with respect to the reference dividing ratio D, apower supply voltage detecting means that detects an inputted powersupply voltage, a pulse width calculating means that outputs the pulsewidth information as A-bit data based upon the power supply voltageinformation and the dividing ratio information obtained at the frequencydividing means, and a pulse width distributing means that outputs dataobtained by adding 1 to the high-order (A-n)-bit data of the A-bit pulsewidth information during nth root of 2 of the distribution pulse thetimes represented by the low-order n-bit of the A-bit pulse widthinformation.

A preferable mode in the above includes the following configuration.Specifically, the pulse width distributing means is configured todistribute a distribution pulse such that the duty ratio of the pulsewidth of the distribution pulse becomes approximately constant, and thefrequency dividing means is configured to include a frequency dividingmeans that divides a clock having a predetermined frequency with thedividing ratio D illustrated by high-order (M-n)-bit data of the M-bitdividing ratio information in order to make the duty ratio of the pulsewidth of the distribution pulse approximately constant and a dividingratio distributing means that outputs 1 during nth root of 2 of thedistribution pulse the times represented by the low-order n-bit of theM-bit dividing ratio information to make the dividing ratio of thefrequency dividing means D+1, wherein the pulse width distributing meansis configured to add 1 to the high-order (A-n)-bit data of the A-bitpulse width information when the output from the dividing ratiodistributing means is 1. Reference is made to an adder 110 in FIG. 33concerning this configuration.

The following configuration is preferable in either of theabove-mentioned means to solve the subjects.

Specifically, the cold cathode tube driving device may also include, infront of the frequency setting means, a current detecting means fordetecting a current flowing through the cold cathode tube that is a loadof the piezoelectric transformer, a rectifying means that converts asinusoidal voltage obtained from the current detecting means into anapproximately DC voltage, an A/D converter that converts the rectifiedvoltage signal into a digital signal, a smoothing process means forsmoothing the output data from the A/D converter and an error voltagecalculating means that multiplies difference data between the externallyapplied reference data and the output data from the smoothing processmeans by a constant and outputs the resultant to the frequency settingmeans as error data.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram schematically showing a configuration of aliquid crystal display device in an embodiment of the present invention;

FIG. 2 is a block diagram showing a cold cathode tube driving deviceaccording to an embodiment 1 of the invention;

FIG. 3 is a timing chart for explaining an operation of the cold cathodetube driving device according to the embodiment 1;

FIG. 4 is a timing chart showing a specific operation of the coldcathode tube driving device according to the embodiment 1;

FIG. 5 is a view for explaining current detection characteristic in thecold cathode tube driving device according to the embodiment 1;

FIG. 6 is a timing chart for explaining a current detection position inthe cold cathode tube driving device according to the embodiment 1;

FIG. 7 is a timing waveform for explaining other averaging process inthe cold cathode tube driving device according to the embodiment 1;

FIG. 8 is a block diagram showing a cold cathode tube driving deviceaccording to a modified mode of the embodiment 1;

FIG. 9 is a block diagram showing a cold cathode tube driving deviceaccording to an embodiment 2 of the invention;

FIG. 10 is a timing chart for explaining an operational concept of thecold cathode tube driving device according to the embodiment 2;

FIG. 11 is a timing chart for explaining other example of the generationof a driving pulse in the cold cathode tube driving device according tothe embodiment 2;

FIG. 12 is a block diagram showing a cold cathode tube driving deviceaccording to a modified mode of the embodiment 2;

FIG. 13 is a block diagram showing a cold cathode tube driving deviceaccording to an embodiment 3 of the invention;

FIG. 14 is a timing chart for explaining an operational concept of thecold cathode tube driving device according to the embodiment 3;

FIG. 15 is a waveform chart showing a lighting detection principle inthe cold cathode tube driving device according to the embodiment 3;

FIG. 16 is a waveform chart for explaining a shift from starting tolighting in the cold cathode tube driving device according to theembodiment 3;

FIG. 17 is a waveform chart for explaining other example of the coldcathode tube driving device according to the embodiment 3;

FIG. 18 is a block diagram showing a cold cathode tube driving deviceaccording to a modified mode of the embodiment 3;

FIG. 19 is a timing chart for explaining an operational concept of thecold cathode tube driving device according to the modified mode of theembodiment 3;

FIG. 20 is a flow chart for explaining a software configuration of thecold cathode tube driving device according to the modified mode of theembodiment 1;

FIG. 21 is a block diagram showing a cold cathode tube driving deviceaccording to a modified mode of the embodiment 4;

FIG. 22 is a timing chart for explaining an operation of a frequencydividing means in the embodiment 4;

FIG. 23 is a block diagram showing a power supply voltage detectingmeans in the embodiment 4;

FIG. 24 is a view showing one example of a relationship between a powersupply voltage and an optimum duty in the embodiment 4;

FIG. 25 is a circuit diagram showing a realized example of a pulse widthadjusting means in the embodiment 4;

FIG. 26 is a timing waveform chart for explaining an operation of thepulse width adjusting means in the embodiment 4;

FIG. 27 is a timing waveform chart for explaining an operation of thepulse width adjusting means in the embodiment 4;

FIG. 28 is a circuit diagram showing another realized example of a pulsewidth adjusting means in the embodiment 4;

FIG. 29 is a timing waveform chart for explaining an operation of thepulse width adjusting means of the another realized example in theembodiment 4;

FIG. 30 is a block diagram showing a configuration of a pulse widthadjusting means of a cold cathode tube driving device according to anembodiment 5 of the invention;

FIG. 31 is a timing chart for explaining an operational concept of thecold cathode tube driving device according to the embodiment 5;

FIG. 32 is a waveform chart showing a principle of the cold cathode tubedriving device in the embodiment 5;

FIG. 33 is a block diagram showing a configuration of a cold cathodetube driving device according to an embodiment 6 of the invention;

FIG. 34 is a circuit diagram showing a realized example of pulse widthdistributing/calculating means in the embodiment 6;

FIG. 35 is a waveform chart for explaining a distribution technique ofthe pulse width distributing/calculating means in the embodiment 6;

FIG. 36 is a waveform chart showing a first distribution example of thepulse width distributing/calculating means in the embodiment 6;

FIG. 37 is a waveform chart showing a second distribution example of thepulse width distributing/calculating means in the embodiment 6;

FIG. 38 is a block diagram obtained by simplifying the pulse widthdistributing/calculating means (FIG. 34) in the embodiment 6;

FIG. 39 is a block diagram of another mode obtained by simplifying thepulse width distributing/calculating means (FIG. 34) in the embodiment6;

FIG. 40 is a view showing frequency characteristic of a piezoelectrictransformer;

FIG. 41 is a principle view of a conventional driving of a piezoelectrictransformer;

FIG. 42 is a waveform chart of each means of the conventionalpiezoelectric transformer driving;

FIG. 43 is a waveform chart for explaining a conventional digitaldriving system;

FIG. 44 is a block diagram realizing a conventional burst dimming;

FIG. 45 is a view for explaining the conventional burst dimming;

FIG. 46 is a waveform chart for explaining a starting method in theconventional burst dimming;

FIG. 47 is a waveform chart for explaining another starting method inthe conventional burst dimming;

FIG. 48 is a waveform chart for explaining a subject in the conventionalpiezoelectric transformer driving;

FIG. 49 is a view showing a resolution of a duty ratio adjustment in theconventional digital-type cold cathode tube driving device;

FIG. 50 is a block diagram realizing a high resolution of a frequencydividing ratio in the conventional digital-type cold cathode tubedriving device; and

FIG. 51 is a waveform chart for explaining an operation for achieving ahigh resolution of a frequency dividing ratio in the conventionaldigital-type cold cathode tube driving device.

BEST MODES FOR CARRYING OUT THE INVENTION

A specific embodiment of a liquid crystal display device according tothe invention will be explained below in detail with reference to thedrawings.

FIG. 1 is a block diagram showing a schematic configuration of theliquid crystal display device having mounted thereto a cold cathode tubedriving device. In FIG. 1, numeral 100 denotes a liquid crystal paneldisplaying an image, 200 a backlight device (including a cold cathodetube 210) with respect to the liquid crystal panel 100, 300 a liquidcrystal driving device that converts an inputted imaging signal into aliquid crystal driving signal and outputs dimming data for controlling abrightness of the backlight device 200 in synchronization with theimaging signal, 400 a backlight driving controller for driving thebacklight 400 and controlling the dimming (hereinafter referred to as adriving controller), 500 a power amplifier for power-amplifying adriving pulse outputted from the driving controller 400, 600 apiezoelectric transformer that drives the cold cathode tube 210 in thebacklight device 200 based upon the driving pulse from the poweramplifier 500, 700 a data converter that electrically detects thedriving state of the cold cathode tube 210 in the backlight device 700and converts the detected result into digital data to be fed back to thedriving controller 400, 800 a one-chip LSI obtained by integrating theliquid crystal driving device 300 with the driving controller 400 and900 a cold cathode tube driving device comprising the driving controller400, power amplifier 500 and data converter 700. The present inventionis structured such that the driving controller 400 is realized in adigital form for making the one-chip LSI incorporating the liquidcrystal driving device 300 and the driving controller 400, therebyenabling a backlight dimming in synchronization with the image andrealizing reduced cost and saved space.

Some preferable embodiments of the invention will specifically beexplained hereinafter. For the sake of convenience, the followingexplanation is made such that the case where power supply voltagevariation does not have to be considered is marked by (A) and the casewhere power supply voltage variation is considered is marked by (B). Thecase (A) includes embodiments 1 to 3, while the case (B) includesembodiments 4 to 6.

(A) Cold Cathode Tube Driving Device/Liquid Crystal Display Devicewherein Power Supply Voltage Variation is not Considered

Embodiment 1

FIG. 2 is a block diagram showing a configuration of the cold cathodetube driving device 900 in the liquid crystal display device accordingto the embodiment 1 of the invention. In FIG. 2, numeral 1 denotes apiezoelectric transformer (corresponding to the piezoelectrictransformer 600 in FIG. 1), 2 a coil, 3 a switching transistor (FET), 4a cold cathode tube (corresponding to the cold cathode tube 210), 5 acurrent detector that detects current flowing through the cold cathodetube 4 and converts the detected result into a voltage signal, 7 arectifying means (e.g., a peak detector circuit) that rectifies asinusoidal voltage signal taken out from the current detector 5 andconverts the resultant into DC voltage and 101 an A/D converter thatconverts the voltage outputted from the rectifying means 7 into adigital signal. Although the current detector 5 is typically representedby a mark of a resistance in the figure, it is not limited to theresistance. The A/D converter 101 has a sufficient number of bits inorder to obtain a voltage detection accuracy and its sampling clock hasa frequency sufficient for assuring a response speed required for thecontrol. An output digital signal from the A/D converter 101 isrepresented by Vad. Numeral 102 denotes an averaging means (preferableexample of smoothing process means) that performs an averaging processto a detection voltage Vad outputted from the A/D converter 101 within apredetermined sample number N (described later). The output digitalsignal from the averaging means 102 is represented by Vave hereinafter.Numeral 103 denotes an error voltage calculating means that compares theoutput signal Vave from the averaging means 102 with externally setreference data Vref, calculates the difference between them and outputsthe resultant as error data Verr. Numeral 104 denotes a frequencysetting means for setting a frequency of a driving pulse of thepiezoelectric transformer 1. This frequency setting means 104 adds orsubtracts the frequency corresponding to the error data Verr to or fromthe previous frequency setting value Fprev, and outputs M-bit dataFnext. This data Fnext means a frequency dividing ratio for the N cycleof the driving pulse. Specifically, the value of Fnext/N becomes anaverage frequency dividing ratio Div of the driving pulse for N cycle.Numeral 121 denotes a controller for generating a control timing pulseat a predetermined period based upon the frequency data Fnext outputtedfrom the frequency setting means 104. This control period is set to theperiod A (A: natural integer) times the N cycle of the driving pulse. Aburst frequency has a period equal to that of the timing pulse outputtedfrom the controller 121. Numeral 105 denotes a frequency dividing meansthat distributes the frequency dividing ratio such that the averagefrequency dividing ratio Div of the driving pulse for N cycle becomesFnext/N to divide a clock. A driving pulse to the piezoelectrictransformer 1 is produced by the frequency dividing means 105. The cyclecomprising the driving pulse for N cycle is a distribution cycle.Numeral 122 denotes a burst pulse generating means that outputs a pulse(hereinafter referred to as a burst pulse) having a duty ratiocorresponding to a dimming level included in the dimming data appliedfrom an external means (the liquid crystal driving device 300 in FIG. 1)based upon the control cycle pulse obtained at the controller 121. Thisburst pulse is set such that “H” level period is not shorter than thedistribution cycle. Numeral 123 denotes an output enabling means thatswitches over the enabling and disabling of the output of the drivingpulse obtained at the frequency dividing means 105. It is configured tobe disabled to stop the driving when the value of the burst pulse is “L”level. The sampling number at the averaging means 102 is set to be equalto the sampling number during the period of the distribution cycle.

The corresponding relationship between FIG. 1 and FIG. 2 is as follows.The coil 2 and the FET 3 constitute the power amplifier 500 thatpower-amplifies the driving pulse outputted from the output enablingmeans 123 and outputs the resultant to the piezoelectric transformer 1.The current detector 5, rectifying means 7 and A/D converter 101constitute the data converter that converts the current flowing throughthe cold cathode tube 4 into digital data. The averaging means 102,error voltage calculating means 103, frequency setting means 104,controller 121, frequency dividing means 105, burst pulse generatingmeans 122 and output enabling means 123 constitute the drivingcontroller 400 that is made by a digital circuit. This drivingcontroller 400 produces a driving pulse that is to be applied to thepiezoelectric transformer 1 based upon the current information in thecold cathode tube 4 outputted from the data converter 700 and theexternally inputted dimming level and the reference data, to therebycontrol the luminous amount of the cold cathode tube 4.

Subsequently explained is the operation of the cold cathode tube drivingdevice 900 in the liquid crystal display device having theabove-mentioned configuration. Firstly, the entire driving concept willbe explained.

The first feature of the present embodiment is that the control cycle isA (A: natural integer) times N cycle of the driving pulse (thedistribution cycle) for driving A times at the same average frequency,and the burst pulse width is set such that its “H” level period is notshorter than the distribution cycle. The second feature is that thesampling number N of the averaging means 102 is set to be equal to thesampling number during the period of the distribution cycle. What ismeant by these two features will be explained with reference to FIG. 3.

FIG. 3 is a timing chart for explaining an operational concept of theembodiment 1. FIG. 3(A) shows the control cycle pulse outputted from thecontroller 121, FIG. 3(B) shows the driving pulse (substantially shownin FIG. 4(C)) outputted from the frequency dividing means 105, FIG. 3(C)shows the burst pulse (by which the on-duty is determined during thecontrol cycle) outputted from the burst pulse generating means 122, FIG.3(D) shows the driving pulse outputted from the output enabling means123, FIG. 3(E) shows the tube current flowing through the cold cathodetube 4, FIG. 3(F) shows the current detection signal outputted from therectifying means 7, FIG. 3(G) shows the data range in which theaveraging process is performed at the averaging means 102 and FIG. 3(H)shows the output data Vave from the averaging means 102. For the sake ofconvenience, the value of A is set to 4. Specifically, there are fourrepeated patterns with the same average frequency 1 (or averagefrequency 2) shown in FIG. 3(B) during one control cycle represented bythe control cycle pulse shown in FIG. 3(A).

The frequency dividing means 105 gets high-precise frequency resolutionat the average frequency for the driving pulse N cycle. Therefore, thepiezoelectric transformer 1 is driven with the driving pulse obtained atthe frequency dividing means 105. Hence, in case where the currentflowing through the cold cathode tube 4 is detected, the detection hasto be made per this distribution cycle unit.

On the other hand, control is performed to make the current duringON-period constant upon the burst driving. When the control is executedper one distribution cycle unit, the burst pulse width (ON-period)becomes shorter than the distribution cycle, so that the current duringthe ON-period cannot be controlled to be constant. Therefore, as shownin FIG. 3(A), driving is performed plural times (plural distributioncycles) at the same average frequency and the burst pulse width(ON-period) is set so as not to be shorter than one distribution cycle,to thereby assure a period for detecting average current during onedistribution cycle. Consequently, in the current detection, the systemof the present invention does not detect current during “H”-level period(ON-period) of the burst pulse like the system disclosed in the document2, but detects the current only during “H”-level period of the burstpulse as well as during the first distribution cycle period (the firstcycle of four distribution cycles) as shown in FIG. 3(G).

The features of the present embodiment were explained above. An actualcontrol flow of the cold cathode tube driving device shown in FIG. 1will be explained below by using specific numerical examples.

In order to simplify the explanation, the distribution cycle is set to 4(N=4) and the control cycle is A times (A 4) the distribution cycle.Further, the resolution of the A/D converter is set to 3-bit and theaimed tube current value is 6.5 obtained by the conversion of thedigital data outputted from the A/D converter 101. Decimal fraction datais not outputted from the A/D converter 101. However, in case where itis considered as the average data during the distribution cycle, decimalfraction exists. Specifically, 11010 (=6.5 wherein upper 3-bit is aninteger means 6, while lower 2-bit 10 is a decimal fraction means) isapplied as the externally applied reference data Vref. In case where theaverage frequency dividing ratio is 5.5 in order to generate the drivingpulse, the frequency data Fnext outputted from the frequency settingmeans 104 is 10110. In this data, the high-order 3-bit represents theinteger means and low-order 2-bit represents the decimal fraction means.Since the distribution cycle N is set to 4, the decimal fraction meansis 2-bit. By this, the driving pulse shown in FIG. 4(C) is outputtedfrom the frequency dividing means 105. In FIG. 4(C), driving pulses offour cycles are illustrated in one distribution cycle, that is thedistribution cycle N. Although there are various methods fordistributing the frequency dividing ratio, no limitation is set here.

FIG. 4(E) shows the tube current waveform when the burst pulse isapplied. As shown in FIG. 4(E), the current value becomes a valuecorresponding to the frequency of the driving pulse. FIG. 4(F) shows anoutput waveform obtained at the rectifying means 7 with the peakdetection after detecting the tube current by the current detector 5. Inthis example, the A/D output data during the distribution cycle isobtained such as “4”, “5”, “4”, “5” as shown in FIG. 4(G). The averagingmeans 102 averages the data of the first distribution cycle((4+5+4+5)/4=4.5), and then outputs the resultant data of 4.5. The errorvoltage calculating means 103 compares the average value 4.5 with theexternally applied reference data (=6.5), and then outputs 2.0(=6.5−4.5) that is the difference data. Subsequently, at the frequencysetting means 104, the output data (=2.0) from the error voltagecalculating means 103 is added to the previous frequency setting value(=6.5) for outputting the next frequency setting data 8.5. This controlis then repeated until the tube current becomes equal to the externallyapplied reference data Vref, whereby the average current can be heldconstant during ON-period.

Here, the average current upon ON-period changes depending strictly uponthe burst pulse width, that will be explained with reference to FIG. 5.FIG. 5(A) shows a distribution example of the frequency dividing ratio.The current according to the frequency dividing ratio flows through thecold cathode tube 4. The current detection period in this example isonly the first distribution cycle as shown in FIG. 5, and the averagefrequency dividing ratio during this cycle is 4.5.

In case where the burst pulse has a pulse width shown in FIG. 5(B), theaverage frequency dividing ratio during this cycle becomes 4.43 (=31/7).In the case of the pulse width shown in FIG. 5(C), its average frequencydividing ratio becomes 4.5 (=27/6), while in the case of the pulse widthshown in FIG. 5(D), its average frequency dividing ratio becomes 4.4(=22/5). In this way, the average current value and the detected currentvalue are actually different. The narrower the burst pulse widthbecomes, the greater the difference becomes.

However, the brightness is greatly influenced by the dimming precisiondue to the burst pulse width. In the example in FIG. 5, the differencesin the brightness level due to the burst pulse width are respectively1/16=6.75%, while the influence due to the error by the currentdetection is (4.5−4.43/4.5)=1.5% in the case of (B), 0% in the case of(C), and only (4.5−4.4)/4.5=2.2% in the case of (D). Further, thefrequency dividing ratio is actually far greater than 4 or 5. In casewhere a pulse of 100 KHz is produced with a clock of 10 MHz, forexample, a clock is required to be divided by 100. This is suggested inFIG. 3(D) in which driving pulses are illustrated in greater detail.Moreover, the frequency dividing ratio is far greater than 4 (e.g., 256distributions). Therefore, the error by the detection becomes a levelthat can nearly be ignored.

As described above, in the present embodiment, the control cycle is Atimes (A: natural integer) N cycle of the driving pulse (distributioncycle) for driving A times at the same average frequency, and thesampling number N at the averaging means 102 becomes equal to thesampling number during the distribution cycle. Therefore, the burstdimming can be realized in the digital driving system using thefrequency distribution of the driving pulse. Consequently, the presentinvention can provide a cold cathode tube driving device using a digitalsystem that is advantageous in reducing cost and saving space because ofone-chip formation with the other LSIs, to thereby bring a great effectto a further miniaturization of a small-sized imaging equipment.

Although the current detection period is set to the first distributioncycle in this embodiment, the current detection period is not limited tothis cycle. This is because the cold cathode tube 4 does not alwaysstart lighting immediately after the voltage is applied thereto.Specifically, some delay occurs upon starting the lighting. Upon theburst driving, the tube current starts to flow after a short time afterthe shift from OFF to ON as shown in FIG. 6(E). Therefore, if thecurrent detection period is set to the first distribution cycle,accurate average current cannot be detected, thus disadvantageous. Inview of this, the detected position may be shifted without changing thedetected width considering the delay time occurred from restarting thedriving to the lighting as shown in FIG. 6(F).

Further, this current detection period is not necessarily set to onedistribution cycle. The current detection period may be varied to have awidth of the double of the distribution cycle or a width of the tripleof the distribution cycle or the like in accordance with the burst pulsewidth as shown in FIG. 7. A block diagram of this case is shown in FIG.8.

In FIG. 8, numeral 124 denotes a detection width adjusting means thatcalculates a detection range from the burst pulse from the burst pulsegenerating means 122 and the control timing pulse from the controller121 for adjusting the detection range in accordance with the burst pulsewidth. In this case, the greater the dimming level becomes, the more thecurrent detection accuracy enhances.

Although the present embodiment utilizes the averaging means to detectthe average current flowing through the cold cathode tube 4 during onedistribution cycle, a normal filter can be replaced with the averagingmeans in case where a strict brightness precision is not required. Theaveraging means or filter means can collectively be referred to assmoothing process means. They are referred to as smoothing process meansin claims of the invention.

Further, each element constituting the driving controller 400 such asthe averaging means 102, error voltage calculating means 103, controller121, frequency setting means 104, burst pulse generating means 122,frequency dividing means 105, output enabling means 123 and detectionwidth adjusting means 124 may be achieved by a hardware or software orby a hybrid structure in combination with a hardware and software.

Embodiment 2

Subsequently explained is a cold cathode tube driving device accordingto the embodiment 2 of the invention. In order to correctly detect theaverage current flowing through the cold cathode tube 4, the detectionrange for a minimum of one distribution cycle is required. In theembodiment 1, the burst pulse width is required to be greater than thedistribution cycle and there is a restriction for the lower limit of thedimming level. The embodiment 2 solves this subject.

FIG. 9 is a block diagram showing a configuration of a cold cathode tubedriving device according to the embodiment 2. Numeral 104 a denotes afrequency setting means for setting a frequency of a driving pulse ofthe piezoelectric transformer 1. This frequency setting means 104 a addsor subtracts the frequency corresponding to the error data Verr to orfrom the previous frequency setting value Fprev, and outputs M-bit dataFnext. The different point from the frequency setting means 104explained in the embodiment 1 shown in FIG. 2 is that, among the M-bitdata showing the frequency dividing ratio including the decimalfraction, the effective bit number in the decimal fraction means isvariable in the embodiment 2 while it is fixed in the embodiment 1. Themethod for varying the effective bit number in the decimal fractionmeans will be made apparent later. Numeral 121 a denotes a controllerfor generating a control timing pulse at a predetermined period basedupon the frequency data Fnext outputted from the frequency setting means104 a. This control period is set to the period A×k times (A is anatural integer, and k is a value varying in accordance with thedistribution cycle) the N cycle of the driving pulse.

Numeral 105 a denotes a frequency dividing means that distributes thefrequency dividing ratio such that the average frequency dividing ratioDiv of the driving pulse for N cycle becomes Fnext/N to divide a clock.The driving pulse of the piezoelectric transformer 1 is produced by thefrequency dividing means. The different point from the frequencydividing means 104 a in the embodiment 1 shown in FIG. 2 is that thevalue N determining the distribution cycle can be set from outside ofthe frequency dividing means. Numeral 125 denotes a distribution numberadjusting means that determines the distribution number from the burstpulse width outputted from the burst pulse generating means 122 and thenoutputs the distribution number N to the frequency dividing means 105 aas well as outputs a change-over signal to the frequency setting means104 a. Further, it sets a value of k to the controller 121 a. The valueof k is determined such that the value (k×N) is made constant so as notto change the control frequency even if the distribution number Nchanges. The other configurations are the same as those in theembodiment 1 shown in FIG. 2, so that the explanation thereof is omittedhere.

Subsequently, the features of the cold cathode tube driving devicehaving the above-mentioned configuration will be explained below. Thefeature of the present embodiment is that the distribution number Nvaries (i.e., the distribution cycle varies) in accordance with theburst pulse width, and the number of driving at the same averagefrequency is simultaneously changed so as not to change the controlcycle (i.e., burst pulse cycle) even if the distribution cycle changes.

This state is shown in FIG. 10. FIG. 10(A) shows that the frequencydividing ratio is distributed so as to obtain an average frequencyaccuracy at N cycle of the driving pulse. In this case, driving isperformed four times at the same average frequency. FIG. 10(B) showsthat the frequency dividing ratio is distributed so as to obtain anaverage frequency accuracy at N/2 cycle of the driving pulse. In thiscase, driving is performed eight times at the same average frequency toachieve the same control cycle as the case shown in FIG. 10(A).

In order to correctly detect the average current flowing through thecold cathode tube 4, the detection range for a minimum of onedistribution cycle is required as explained in the embodiment 1. In thecase of FIG. 10(A), a minimum of 25% of the burst pulse duty is requiredto assure the detection during one distribution cycle, while 12.5% isenough in the case of FIG. 10(B). On the other hand, the currentaccuracy is higher as the distribution number is great, so that thecurrent accuracy in FIG. 10(B) is half that in FIG. 10(A).

However, requiring the dimming precision is normally a dimming level ofabout 50 to 100% used for an image appreciation. A low brightness meansdoes not require the dimming precision compared to a high brightnessmeans. A low brightness mode is used to reduce power consumption whenonly a stand-by mode or OSD (on-screen display) is displayed. In thecase of the low brightness (in case where the burst pulse width is notmore than the predetermined value), the distribution number is madesmall and the number of times for driving with the same frequencyincreases so as not to change the burst frequency.

As described above, changing the distribution number in accordance withthe burst pulse width enables to lower the dimming level, thereby beingcapable of enlarging the dimming range.

Although the explanation is made here as to the method for changing thedistribution number in order to lower the dimming level, there is ofcourse a method for changing the burst frequency in case where theflicker caused by the reduction in the burst frequency can be avoided.In this case, the number of times A of the distribution cycle driven atthe same frequency may be changed with the distribution number constantas shown in FIG. 11.

FIG. 12 shows the embodiment of this case. In FIG. 12, numeral 121 bdenotes a controller configured such that the number of times A drivenat the same frequency can be set from outside of the controller andnumeral 126 denotes a control cycle setting means that sets the drivingtimes A of the controller 121 b in synchronization with the burst pulse.It increases the amount of A to lower the MIN dimming level in casewhere the dimming level reaches not more than the predetermined level.The configuration shown in FIG. 12 brings an effect of greatly enlargingthe detection range compared to the embodiment 1, although the burstfrequency (ON/OFF frequency) varies.

Although special reference is not made here, the present embodiment mayadopt a means for changing the detection range according to the duty ofthe burst pulse or adopt the replacement of the averaging means with asimple filter means as explained in the embodiment 1.

Further, each element constituting the driving controller 400 such asthe averaging means 102, error voltage calculating means 103, controller121, frequency setting means 104 a, burst pulse generating means 122,frequency dividing means 105 a, output enabling means 123, distributionnumber adjusting means 125 and control cycle setting means 126 may beachieved by a hardware or software or by a hybrid structure incombination with a hardware and software.

Embodiment 3

Subsequently, a cold cathode tube driving device according to anembodiment 3 of the invention will be explained.

FIG. 13 shows a block diagram showing a configuration of the coldcathode tube driving device according to the embodiment 3 of theinvention. This embodiment provides a cold cathode tube driving devicethat does not deteriorate a lighting performance and lighting quality atthe starting even if the dimming level is low.

In FIG. 13, numeral 14 denotes voltage detecting means for detecting anoutput voltage from the piezoelectric transformer 1, and 15 a shieldingmeans for turning on or off the detected voltage of the piezoelectrictransformer 1 detected by the voltage detecting means 14. The shieldingmeans is configured such that the output voltage therefrom becomes at“L” level when the detected voltage is turned off. Numeral 7 a denotes apeak detecting means for detecting the output voltage of thepiezoelectric transformer 1 outputted from the shielding means 15 andthe maximum tube current outputted from the current detector 5. Thecurrent detector 5, peak detecting means 7 a, voltage detecting means14, shielding means 15 and A/D converter 101 constitute a data converter700 a that time-sharingly detects the current flowing through the coldcathode tube 4 and the output voltage of the piezoelectric transformer 1and converts the resultant into digital data. Numeral 127 denotes alighting detecting means for performing a lighting detection from thedigital output data from the A/D converter 101. It executes ON/OFFcontrol of the shielding means 15 at a predetermined period forperforming the lighting detection. The lighting detecting means 127 isconfigured to output a detection switching pulse to the shielding means15 and output a lighting detection pulse to a dimming level switchingmeans 128 and a control cycle switching means 129 described later. Thislighting detecting means 127 will be explained later in detail.

Numeral 128 denotes the dimming level switching means for changing overthe dimming level applied to the burst pulse generating means 122 basedupon the lighting detection pulse outputted from the lighting detectingmeans 127. It is configured to output the previously set dimming levelat the starting. It is to be noted here that the dimming level at thestarting is 100% (continuous driving).

Numeral 121 b denotes a controller that can set the number of times Afor driving at the same frequency from the outside. This controller issame as that shown in FIG. 12. Numeral 126 a denotes a first controlcycle setting means for setting a first control cycle of the controller121 b, while numeral 126 b denotes a second control cycle setting meansfor setting a second control cycle of the controller 121 b. Numeral 129denotes the control cycle switching means that performs a change-overbetween control cycle information outputted from the first control cyclesetting means 126 a and control cycle information outputted from thesecond control cycle setting means 126 b based upon the lightingdetection pulse outputted from the lighting detecting means 127, andoutputs the resultant. As described above, the control cycle outputtedto the frequency setting means 104 is changed over between at thestarting and at the lighting. The first control cycle setting means 126a sets the control cycle at the starting. The control cycle set by thefirst control setting means 126 a is set to correspond to twodistribution cycles (the amount of A is 2). The second control cyclesetting means 126 b sets the control cycle at the lighting. Its cycle isset to correspond to four distribution cycles (the amount of A is 4)like the embodiment 1. The other configurations are the same as those inthe embodiment 1 explained by using FIG. 2, so that their explanationsare omitted here.

A driving controller 400 c is configured by the averaging means 102,error voltage calculating means 103, frequency setting means 104,controller 121 b, frequency dividing means 105, burst pulse generatingmeans 122, output enabling means 123, lighting detecting means 127,dimming level switching means 128, first control cycle setting means 126a, second control cycle setting means 126 b and control cycle switchingmeans 129, those of which are configured as described above.

Subsequently explained are features of the cold cathode tube drivingdevice of the present embodiment shown in FIG. 13 having theabove-mentioned configuration. The features of the present embodimentare as follows.

(1) A continuous driving is performed at the starting that can assurethe lighting performance, and after the detection of the lighting, adimming level is promptly shifted to a desired level.

(2) The detection of the lighting is performed within the burst pulsewidth at the MIN dimming in order to suppress the variation in thebrightness immediately after the lighting.

In order to realize the feature (2), in particular, the control cycle ischanged over between at the starting and at the lighting, and thecontrol cycle at the starting is made shorter.

Firstly, FIG. 14 shows control cycles at the starting and lighting. FIG.14(A) shows a driving pulse during one control cycle at the starting,i.e., driving is performed two times at the same average frequency. FIG.14(C) shows a driving pulse during one control cycle at the lighting,i.e., driving is performed four times at the same average frequency.FIG. 14(B) shows a voltage (current) detection period at the starting.The detection is made with the delay A shifted. FIG. 14(D) shows avoltage (current) detection period at the lighting. The detection ismade with the delay A shifted like the case at the starting.

Subsequently explained is the operation of the lighting detecting means127 for making the change-over from the control at the starting to thecontrol at the lighting. FIG. 15 shows the operation of the lightingdetecting means 127 at the starting. FIG. 15(C) shows an output voltagedetection signal of the piezoelectric transformer 1 outputted from thevoltage detecting means 14, while FIG. 15(D) shows a current detectionsignal outputted from the current detector 5. The current does not flowat the starting since the cold cathode tube 4 is not lit. The controlcycle setting means 129 selects the first control cycle setting means126 a, so that the control cycle corresponding to two same drivingperiods is set. The dimming level switching means 128 selects thedimming level of the continuous driving and outputs the selectedresultant to the burst pulse generating means 122.

FIG. 15(E) shows a change-over pulse that is a detection pulse outputtedto the shielding means 15 from the lighting detecting means 127 fordetecting the lighting. When this change-over pulse is at “H” level, theshielding means is turned OFF, and a peak value of the current detectionsignal is outputted from the peak detecting means 7 a. The detection ofthe lighting is determined by the output level of the peak detectingmeans 7 a when the change-over pulse is at “H” level. Specifically, theoutput from the peak detecting means 7 a is at zero level at thenon-lighting period since the tube current does not flow, while the tubecurrent flows when the lighting is started, so that the voltagecorresponding to the tube current is outputted from the peak detectingmeans 7 a. Therefore, if the change-over pulse is at “H” level, thelighting is not executed when the output from the peak detecting means 7a is at “L” level, while the lighting is determined to be performed whenthe output from the peak detecting means 7 a is not less than thepredetermined level.

In FIG. 15, the lighting is started at a time T1, whereupon the tubecurrent starts to flow as shown in FIG. 15(D). Next, at a time T2, theoutput from the peak detecting means 7 a becomes to a level correspondto the tube current when the change-over pulse shown in FIG. 15(E) is at“H” level, whereby the lighting is detected. As a result, the lightingdetection pulse shown in FIG. 15(G) shifts from “L” level to “H” level.

Subsequently, FIG. 16 shows each waveform when the control at thestarting is shifted to the control at the lighting. As shown in FIG. 16,the cold cathode tube 4 starts to light at the time T1, so that the tubecurrent starts to flow. At the time T2 immediately after the time T1,the lighting is detected by the change-over pulse, whereby the lightingdetection pulse shifts from “L” level to “H” level.

When the lighting detection pulse is at “H” level at the time T2, thecontrol cycle switching means 129 is switched to a state for selectingthe second control cycle setting means 126 b. By this, the control cycleis changed from the cycle corresponding to two same driving periods tothat corresponding to four same driving periods. Simultaneously, thedimming level switching means 128 changes the dimming level for thecontinuous driving to the externally applied dimming level, and outputsthe resultant to the burst pulse generating means 122. By thisoperation, the burst pulse is outputted from the time T2 as shown inFIG. 16(H), to thereby change the dimming to the burst dimming. In thisprocess, there is an irregular period in the tube current before andafter the lighting as shown in FIG. 16(D), whereby the brightness changecorresponding to this irregular period occurs. However, this period issuppressed to as much as 50% of the control cycle at the lightingperiod, so that the brightness change at the lighting period is greatlyimproved in the actual use. Further, the control cycle at the lightingperiod is not actually 4. For example, in case where the burst frequencyis 150 Hz, the driving frequency of the piezoelectric transformer 1 is150 KHz and the distribution number is 100, the distribution frequency(1/distribution cycle) is 150 KHz/100=1.5 KHz. In order to obtain theburst frequency of 150 KHz, the control cycle becomes ten times thedistribution cycle. In this case, the maximum irregular period is 20% ofthe control cycle at the lighting period as shown in FIG. 17. The changein the brightness level at this time can actually be neglected.

Further, making the distribution number at the starting smaller than thedistribution number at the lighting further shortens the irregularperiod, to thereby be capable of obtaining a satisfactory lightingperformance. FIG. 18 shows this example.

In FIG. 18, numeral 125 a denotes a distribution number adjusting meansfor performing the change-over of the distribution cycle from thefrequency setting means 104 a. The frequency setting means 104 aperforms the same operation as the frequency setting means shown in FIG.9 in the embodiment 2. Specifically, the distribution number changesdepending upon the output from the distribution number adjusting means125 a. The different point from the distribution adjustment means 125shown in FIG. 9 in the embodiment 2 is that the distribution numberadjusting means 125 a in this embodiment is configured to change thedistribution number between at the lighting and at the starting, whilethe distribution number adjusting means 125 in the embodiment 2 changesthe distribution number in accordance with the burst pulse width fromthe burst pulse generating means 122, i.e., in accordance with thedimming level. Therefore, the lighting detection pulse from the lightingdetecting means 127 is inputted to the distribution number adjustingmeans 125 a. The other operations are the same as those shown in FIG.13.

FIG. 19 shows each waveform of each means from the starting to thelighting. The lighting detection period in this embodiment at thestarting is one half the period in the embodiment shown in FIG. 13,whereby the irregular period at the starting at the lighting period is ahalf the period shown in FIG. 13.

As described above, according to the cold cathode tube driving device ofthe embodiment 3 of the invention, the continuous driving is executed atthe starting, thereby being capable of shifting to the burst dimmingwithout deteriorating the lighting performance. Further, changing thecontrol cycle at the starting and at the lighting, or changing thedistribution number can improve the brightness change at the lighting toa level almost neglected, thereby giving an effect of remarkablyimproving the lighting quality.

Each element constituting the driving controller 400 c such as theaveraging means 102, error voltage calculating means 103, controller 121b, frequency setting means 104, burst pulse generating means 122,frequency dividing means 105, output enabling means 123, lightingdetecting means 127, dimming level switching means 128, first controlcycle setting means 126 a, second control setting means 126 b, controlcycle switching means 129 and distribution number adjusting means 125 amay be achieved by a hardware or software or by a hybrid structure incombination with a hardware and software.

The other features of the above-mentioned embodiments 1 to 3 are thatthe device may be controlled by a software since the processing by thedriving controller can be digitized. Specifically, the control can beachieved by a microcomputer program, to thereby be capable of easilyestablishing a system.

FIG. 20 shows a flow chart taking the case of the embodiment 1 as anexample.

In FIG. 20, step S1 shows a data-read process. Step S2 determineswhether data-fetch number reaches a predetermined number or not. If itdoes not reach the predetermined number, the process returns to the stepS1 for fetching data again. If it reaches the predetermined number, theaverage of the data obtained at the step S3 is calculated. Thepredetermined number means here a driving pulse number that is amultiple of the distribution cycle. These steps S1 to S3 correspond tothe averaging means 102 shown in FIG. 2 in the embodiment 1. Step S4compares externally applied reference data with average data. The stepS4 corresponds to the error voltage calculating means 103 in theembodiment 1. If the reference data is greater than the average data,the next frequency dividing ratio is set rather great (so as to reducethe driving frequency) at step S5 in order to increase the currentflowing through the cold cathode tube 4. On the other hand, if thereference data is smaller than the average data, the frequency dividingratio is set rather small at step S6 in order to decrease the currentflowing through the cold cathode tube 4. The steps S5 and S6 correspondto the frequency setting means 104 shown in FIG. 2. Step S7 divides aclock (corresponding to a microcomputer clock or a timer formed of themicrocomputer clock on a software) at the set frequency dividing ratio.This corresponds to the frequency dividing means 105 shown in FIG. 2.Step S8 counts the number of the divided data (corresponding to thedriving pulse) for determining whether the distribution number of timesreaches the predetermined number. If it does not reach the predeterminednumber, the process returns to the step S7 to perform the dividing atthe same frequency setting once again. This means corresponds to thecontroller 121 in FIG. 2. Thereafter, a burst pulse width is calculatedat step S9 based upon the externally applied dimming level. When theburst pulse is at “H” level, the above-mentioned divided data isoutputted from an output port, while the output port is set to “L” levelwhen the burst pulse is at “L” level. This means corresponds to theburst pulse generating means 122 in FIG. 2. The steps S10 to S12correspond to the output enabling means 123 in FIG. 2.

The operation on the software was simply explained above by taking theembodiment 1 shown in FIG. 2 as an example. The processing by a softwareis possible in the other embodiments, although specific examples are notillustrated here.

(B) Cold Cathode Tube Driving Device/Liquid Crystal Display Devicewherein Power Supply Voltage Variation is Considered

Required to the piezoelectric transformer for driving the cold cathodetube that is the backlight basically are dimming function, low electricpower (high power conversion efficiency) or the like. Further, in casewhere it is used in portable equipment such as a notebook-sized personalcomputer or a digital video camera, stable lighting and stable powerconversion efficiency are desired within a wide range of a power supplyvoltage considering a battery source from which a stable source cannotbe obtained.

In order to improve the above subject, Japanese Unexamined PatentPublication No. HEI8-33349 discloses a method for changing a pulse width(duty ratio) of a driving pulse in accordance with a power supplyvoltage to cope with a wide power supply voltage range. This method isreferred to as a duty control below.

The principle disclosed in the document 3 will briefly be explained withreference to FIGS. 48(A) and 48(B). FIG. 48(A) shows a driving pulseapplied to a gate of an FET that is a switching transistor of apiezoelectric transformer, and FIG. 48(B) shows a drain voltagegenerated by the driving pulse. This drain voltage varies depending uponthe power supply voltage. When the power supply voltage rises, theamplitude of the drain voltage increases as shown in (C), whereby theFET is turned ON before the drain voltage becomes 0 V. In this state,great current (surge current) flows by short-circuiting the drain andGND the moment the FET is turned ON. This leads to a breakdown of theFET. When this rapid current flows through the piezoelectrictransformer, the piezoelectric transformer may be broken down.Therefore, the driving pulse width is adjusted in accordance with thepower supply voltage so as to prevent the rapid surge current fromflowing.

FIG. 48(D) shows a driving pulse in case where the power supply voltageincreases. This driving pulse is set to have a width smaller than thatof the driving pulse shown in (A). By this setting, the FET is turned ONat the drain voltage of 0 V as shown in (E). This method enables adriving with reduced loss even within a wide power supply voltage range.

As described above, the document 3 discloses the method for varying theduty ratio of the driving pulse in accordance with the power supplyvoltage, to thereby enable the use within a wide power supply voltagerange.

However, in case where this method is performed in a digital drivingsystem, the resolution in the duty ratio is rough by a clock of on theorder of 10 MHz, whereby a sufficient performance cannot be obtained.(Raising the clock frequency can assure the resolution, but it causesincreased circuit power or increased radiated interference, thusunpractical.) Therefore, it is desired that the duty ratio of thedriving pulse can be adjusted in intervals of as small as possible forobtaining a satisfactory performance within a wide power supply voltagerange. Specifically, the duty ratio can desirably be varied in at least0.1-V steps of the power supply voltage.

FIG. 49 shows a case wherein the duty ratio is adjusted in a digitaldriving system. The lower the frequency of the clock becomes, therougher the resolution becomes, so that there occurs a point greatlydeviating from the ideal.

Explanation is made by citing an example. In case where a clock of 10MHz is divided into 100 to produce a driving pulse having a frequency of100 kHz, the pulse width of the produced pulse can be adjusted every onecycle from 1 cycle width to 99 cycle widths. Specifically, the dutyratio can be adjusted in 1-% steps.

However, in case where the ideal duty curve has the duty ratio of 30% to20% at the power supply voltage of 5 V to 10 V, for example, only10-step adjustment (in 0.5-V steps) can be performed in 1-% steps, thatcannot afford a sufficient performance.

An embodiment 4 and the following embodiments of the invention areaccomplished in view of the above-mentioned subject, and propose a dutycontrol system in a digital driving system without deteriorating anefficiency for aiming to realize a cold cathode tube driving devicecoping with a power supply voltage of a wide range.

Embodiment 4

FIG. 21 is a block diagram showing a configuration of a cold cathodetube driving device according to the embodiment 4 of the invention. InFIG. 21, numeral 1 denotes a piezoelectric transformer, 2 a coil, 3 aswitching transistor (FET), 4 a cold cathode tube, and 5 a currentdetector that detects current flowing through the cold cathode tube 4and converts the detected result into a voltage signal. Although thecurrent detector 5 is representatively illustrated by a mark of aresistor, it is not necessarily be a resistor. Numeral 7 denotes arectifying means that rectifies a sinusoidal voltage signal taken outfrom the current detector 5 and converts the resultant into DC voltageand 101 an A/D converter (a first A/D converter) that converts thevoltage outputted from the rectifying means 7 into a digital signal. TheA/D converter 101 has a sufficient number of bits in order to obtain avoltage detection accuracy and its sampling clock has a frequencysufficient for assuring a response speed required for the control. Anoutput digital signal from the A/D converter 101 is represented by Vad.Numeral 102 denotes a smoothing process means that performs a smoothingprocess to a detection voltage Vad outputted from the A/D converter 101within a predetermined sample number. The output digital signal from thesmoothing process means 102 a is represented by Vave hereinafter.Numeral 103 denotes an error voltage calculating means that compares theoutput signal Vave from the smoothing process means 102 a withexternally set reference data Vref, calculates the difference betweenthem and outputs the resultant as error data Verr. Numeral 104 denotes afrequency setting means for setting a frequency of a driving pulse ofthe piezoelectric transformer 1. This frequency setting means 104 addsor subtracts the frequency corresponding to the error data Verr to orfrom the previous frequency setting value Fprev, and outputs M-bit dataFnext. This data Fnext means a frequency dividing ratio for the N cycleof the driving pulse. Numeral 105 denotes a frequency dividing meansthat distributes the frequency dividing ratio such that the averagefrequency dividing ratio Div of the driving pulse for N cycle becomesFnext/N to divide a clock. A driving pulse to the piezoelectrictransformer 1 is produced by the frequency dividing means 105. Thedriving pulse for distributing the frequency dividing ratio outputtedfrom the frequency dividing means 105 is represented by pzpls.

FIG. 22(B) shows an example of the distribution pulse pzpls produced atthe frequency dividing means 105, while FIG. 22(C) shows frequencydividing ratio data that is simultaneously obtained. Further, FIG. 22(A)shows a clock.

The configuration described so far is the same as that disclosed in thedocument 1 (Japanese Unexamined Patent Publication No. 2000-133485), andits operation is the same. The feature of this embodiment is that thedevice of this embodiment includes the following means 106 to 108.

Numeral 106 denotes a power supply voltage detecting means that detectsa power supply voltage and outputs the detected voltage as a digitalvalue. The power supply voltage detecting means is configured as shownin FIG. 23, for example. In FIG. 23, numerals 106 a and 106 b denoteresistors that divides the power supply voltage and converts the dividedpower supply voltage into a voltage that adapts to an input dynamicrange of a second A/D converter 106 c. The second A/D converter 106 cconverts the inputted voltage into a digital value. The output signalfrom the power supply voltage detecting means 106 is represented byVpwr.

Numeral 107 denotes a pulse width calculating means that calculates aduty value (hereinafter referred to as Vduty) of the driving pulse fromthe frequency data Fnext obtained at the frequency setting means 104 andthe power supply voltage information Vpwr obtained at the power supplyvoltage detecting means 106 based upon a relationship between apredetermined power supply voltage and duty value of the driving pulse.The duty ratio of the pulse width means a ratio of “H”-level period and“L”-level period. This duty ratio of the pulse width corresponds topulse width information.

For example, FIG. 24 shows one example of a relationship between thepower supply voltage and the duty value of the driving pulse. There arevarious calculation methods of the pulse width calculating means 107,and special limitation is not made here to the calculation method. Thevarious calculation methods include, for example, a ROM method in whichthe relationship between the power supply voltage Vpwr and the dutyvalue Vduty is stored in advance in a ROM (read-only memory) or a methodfor calculating a curve shown in FIG. 24 by using a linearapproximation.

Numeral 108 denotes a pulse width adjusting means for adjusting thepulse width based upon the duty value Vduty outputted from the pulsewidth calculating means 107.

FIG. 25 shows an example of a specific configuration of the pulse widthadjusting means 108. In FIG. 25, numeral 108 a denotes a pulse widthshaping means (decode means) that converts the inputted distributionpulse pzpls into a pulse width according to the duty value Vduty.

When the duty value Vduty is A-bit digital data, data of high-order(A-1)-bit is referred to at the pulse width shaping means 108 a and asignal of a pulse width equal to the value of (A-1)-bit is outputted.

The data of the high-order (A-1)-bit from 0th-bit to (A-1)th-bit of thesignal Vduty having a bus width of A-bit is represented by Vduty[A-1:1].The data of the least significant bit is represented by Vduty[0].

FIG. 26 shows input/output waveform of the pulse width shaping means 108a. As shown in FIG. 26(D), the pulse width of the outputted pulse isequal to the value of Vduty[A-1:1] shown in FIG. 26(C).

Numeral 108 b denotes a D-type flip-flop (hereinafter referred to asDFF) that latches and outputs an output signal from the pulse widthshaping means 108 a. This output signal is represented by an initialpulse pzplsa. Numeral 108 c denotes a DFF that latches the initial pulsepzplsa at the trailing edge of the clock and outputs the resultant. Thisoutput signal is represented by a pulse pzplsb. Numeral 108 d denotes anOR gate. The output signal from the OR gate is represented by anextended pulse pzplsc. These DFF 108 c and OR gate 108 d constitute apulse width extending means 108 g. Specifically, the pulse width isextended by carrying out the logical sum after delaying. Numeral 108 edenotes a selector that outputs the extended pulse pzplsc when theVduty[0] is 1 while outputs the initial pulse pzplsa when the Vduty[0]is 0. The output from the selector 108 e becomes a driving pulse pzdrvfor driving the FET 3. Numeral 108 f denotes an inverter for inverting aclock. Attention has to be paid on a point that the clock is inverted bythis inverter 108 f and then latched by the DFF 108 c at the trailingedge of the clock.

Subsequently explained is the operation of the cold cathode tube drivingdevice having the above-mentioned configuration shown in FIGS. 21 and25. The operation will be explained centering on the feature of thisembodiment.

The feature of the present embodiment is a technique for doubling theresolution in the pulse width of the driving pulse pzdrv by using thetrailing edge of the clock.

A normal digital LSI is generally configured by a synchronous circuit inwhich a process from designing, proving to manufacturing is established.Therefore, such a synchronous circuit does not use a trailing edge of aclock that is an asynchronous processing. However, this asynchronousprocessing can relatively easily be proved immediately before an outputpin of the LSI, so that the processing using the trailing edge can beexecuted at a final stage of the circuit.

Specifically, the duty value Vduty of the pulse width informationoutputted from the pulse width calculating means 107 is divided intohigh-order bits and low-order bits. The high-order bits of the dutyvalue Vduty are used at a first stage to produce a pulse having apredetermined pulse width in the normal synchronous processing. Further,the low-order bits of the duty value Vduty are used at a second stage toincrease the resolution by a process using the trailing edge of theclock. After the process of the second stage, the synchronous processingis not performed.

FIG. 27 shows waveforms for producing pulse widths in two stages. FIG.27(A) shows a clock, (B) the distribution pulse pzpls from the frequencydividing means 105, (C) the duty value Vduty, (D) data Vduty[A-1:1]showing high-order (A-1)-bit of the duty value Vduty, and (E) the dataVduty[0] showing the least significant bit of the Vduty.

In case where the Vduty is 10, i.e., (1010)₂ in a binary notation, forexample, the data Vduty[A-1:A] showing the high-order [A-1]-bit is(101)₂ that is 5, while the data Vduty[0] showing the least significantbit is (0)₂ that is 0. Further, in case where the Vduty is 9 that is(1001) ₂ in the binary notation, the data Vduty[A-1:A] showing thehigh-order (A-1)-bit is (100)₂ that is 4, while the data Vduty[0]showing the least significant bit is (1)₂ that is 1.

In FIG. 27, (F) shows the initial pulse pzplsa that is obtained bylatching the pulse outputted from the pulse width shaping means 108 a atthe leading edge of the clock, while (G) shows the pulse pzplsb that isobtained by latching the initial pulse pzplsa at the trailing edge ofthe clock.

Firstly, the first-stage pulse width producing process is performed atthe pulse width shaping means 108 a. The pulse width at this time is theVduty[A-1:A] obtained by dividing the Vduty by 2 and discarding thedecimals.

For example, the Vduty[A-1:A] is 5 when the Vduty is 10, while theVduty[A-1:A] is 4 when the Vduty is 9.

The pulse width extending means 108 g constituted by the DFF 108 c andthe OR gate 108 d performs a process for extending the pulse width ofthe initial pulse pzplsa by 0.5 cycles of the clock. FIG. 27(H) showsthe extended pulse pzplsc obtained by this process.

Subsequently, the selector 108 e outputs the extended pulse pzplsc thatis wider by 0.5 cycles when the value of Vduty[0] is 1, i.e., thediscarded value is 1. On the other hand, the selector 108 e outputs theinitial pulse pzplsa when the value of Vduty[0] is 0, i.e., there is nodiscarded value (the discarded value is 0). By this process, theobtained driving pulse pzdrv has a pulse width according to the value ofVduty, such as a width of 5 cycles, a width of 4.5 cycles, and a widthof 5 cycles as shown in FIG. 27(I). Specifically, when the Vduty is 10,the pulse width is 5 that is a half of the Vduty. Likewise, when theVduty is 9, the pulse width is 4.5 that is a half of the Vduty. Around-off process is not performed, whereby the pulse width correctlycorresponds to a half of the Vduty to thereby enhance the resolution.

This driving pulse pzdrv is outputted not via the synchronizationcircuit but directly from a pin, thereby not bringing a problem upondesigning and proving a digital LSI.

As described above, the present embodiment can provide a pulse widthresolution with a double precision by using a trailing edge of a clockwithout deviating from a designing technique of a digital LSI, whereby adriving pulse having an optimum pulse width can be obtained within awide range of a power supply voltage even in a digital driving system.This leads to reduce a power consumption due to an improvement inefficiency and to prevent a break-down of an FET or piezoelectrictransformer because of a surge upon driving the piezoelectrictransformer, thereby bringing a great effect.

Although the above-mentioned embodiment utilizes a trailing edge of aclock, a delay element can be combined to be used.

FIG. 28 shows an example of a pulse width adjusting means in which adelay element is used in combination with a method using the trailingedge of the clock.

In FIG. 28, numerals 108 g 1 and 108 g 2 denote delay elements. Thedelay amount of the delay elements is set to a fourth of one cycle of aclock. Numeral 108 d 1 to 108 d 3 denote OR gates, and 108 e 1 to 198 e3 selectors. The other configurations are the same as those of the pulsewidth adjusting means shown in FIG. 25. In FIG. 25, the duty value Vdutyis A-bit, Vduty[A-1:1] is inputted to the pulse width shaping means 108a and a fine adjustment of the pulse width is performed by using atrailing edge of a clock at Vduty[0]. On the other hand, in FIG. 28, theduty value Vduty is (A+1)-bit, Vduty[A:2] that is high-order (A-1)-bitis inputted to the pulse width shaping means 108 a and a fine adjustmentis performed at Vduty[1:0] that is low-order 2-bit of the duty valueVduty.

This will be explained below with reference to FIG. 29 showing timingwaveform charts of each means.

In FIG. 29, (F) shows a pulse pzplsa latched at a leading edge of aclock at the pulse width shaping means 108 a generating a driving pulsehaving a pulse width determined by the value of Vduty[A:2] and thenoutputted therefrom. This pulse is approximately the same as the oneexplained in the embodiment 4 with reference to FIG. 25. This pulsepzplsa is delayed by 1/4 cycles of a clock by the delay element 108 g 1,to thereby obtain a waveform shown in FIG. 29(G). FIG. 29(H) shows apulse pzplsb obtained by latching the pulse pzplsa at a trailing edge ofa clock. This pulse pzplsb is the same as the one explained in FIG. 25.Further, this pulse pzplsb is delayed by the delay element 108 g 2,whereby a signal shown in FIG. 29(I) delaying by 1/4 cycles of a clockwith respect to the pulse pzplsb is obtained. These signals respectivelypass through the OR gates 108 d 1 to 108 d 3, to thereby obtain threeextended pulses pzplsc1, pzplsc2 and pzplsc3, the pulse widths of thesepulses becoming gradually wider in this order in steps of a resolutionof 1/4 clock cycles with respect to the initial pulse pzplsa as shown inFIGS. 29(J) to (L). The selectors 108 e 1 to 108 e 3 perform achange-over between the pulse pzplsa and pulses pzplsc1 to pzplsc3 inaccordance with the value of Vduty[1:0] and outputs the resultant to theFET 3. When the Vduty[1:0] is 0, the pulse pzplsa having the narrowestpulse width is selected. When the Vduty[1:0] is 1, the pulse pzplsc1having the second narrowest pulse width is selected. When the Vduty[1:0] is 2, the pulse pzplsc2 having the third narrowest pulse width isselected. When the Vduty[1:0] is 3, the pulse pzplsc3 having the widestpulse width is selected. FIG. 29(M) shows a driving pulse pzdrvoutputted to the FET 3.

Specific examples are illustrated below. When Vduty=21=(10101)₂,Vduty[A:2]=(101)₂=5 and Vduty[1:0]=(01)₂=0. The cycle of the drivingpulse pzdrv is 5.25 cycles at this time, that is just equal to the valueobtained by dividing 21 by 4. Further, When Vduty=20=(10100) ₂,Vduty[A:2]=(101) ₂ ₌₅ and Vduty[1:0]=(00) ₂=0. The cycle of the drivingpulse pzdrv is 5 cycles at this time, that is just equal to the valueobtained by dividing 20 by 4. Further, When Vduty=19=(10011)₂,Vduty[A:2]=(100)₂=4 and Vduty[1:0]=(11)₂=3. The cycle of the drivingpulse pzdrv is 4.75 cycles at this time, that is just equal to the valueobtained by dividing 19 by 4. Although not shown in the figure, whenVduty 18 (10010)₂, Vduty[A:2]=(100)₂=4 and Vduty[1:0]=(10)₂=2. The cycleof the driving pulse pzdrv is 4.5 cycles at this time, that is justequal to the value obtained by dividing 18 by 4.

The configuration shown in FIG. 28 provides, in addition to theenhancement in the resolution of pulse width by using a trailing edge ofa clock, the resolution double the former resolution by using the delayelements 108 g 1 and 108 g 2 that delay a pulse by 1/4 cycles of aclock. Therefore, this configuration can provide a resolution having afourfold precision, thereby enabling a control of pulse width withhigher precision.

The method using the delay element needs the following attentions. Thedelay cycle generally varies depending upon a temperature or powersupply voltage. Therefore, uniform resolution cannot be obtained when atemperature or power supply voltage varies. For example, the delay cyclemay vary like “0.1”, “0.5”, “0.6”, “1.0”, . . . that must originally bevaried like “0.25”, “0.5”, “0.75”, “1.0”, . . . .

The delay amount of the delay element is set to 1/4 cycles of a clock inthis technique. However, when the clock frequency changes, the delayamount does not change in synchronization with this change. Accordingly,the following processes are required such that the delay element is usedwith a fixed clock frequency, or a plurality of delay elements areprovided and switched over between them depending upon the clockfrequency.

Although there are the above-mentioned restrictions in the method usingthe delay element, it assuredly enhances the resolution. Therefore, thismethod is effective for the case where a sufficient effect cannot beobtained by using the trailing edge of the clock.

The method using the trailing edge of a clock can provide a uniformresolution even if conditions are changed, since the delay amount doesnot change depending upon a temperature or power supply voltage in thismethod.

Although FIG. 28 shows an example obtained by combining a process by atrailing edge of a clock with a delay element, a configuration usingonly a delay element, not using a trailing edge of a clock can providean effect, since the process by the trailing edge of a clock has thesame function as the delay element.

Each element such as the averaging means 102 a, error voltagecalculating means 103, frequency setting means 104, frequency dividingmeans 105, pulse width calculating means 107 and pulse width adjustingmeans 108 may be achieved by a hardware or software or by a hybridstructure in combination with a hardware and software.

Embodiment 5

Subsequently explained is a cold cathode tube driving device accordingto an embodiment 5 of the invention. The embodiments shown in FIGS. 25and 28 are effective to produce a pulse width having high resolution.However, they cannot be utilized as they are in case where the dividingratio utilizes a trailing edge of a clock to enhance the resolution ofthe driving frequency as disclosed in Japanese Unexamined PatentPublication No. 2000-139081 (Document 4). Accordingly, the presentembodiment provides a technique capable of effectively enhancing theresolution in a pulse width of a driving pulse even in case where thedividing ratio utilizes a trailing edge of a clock.

FIG. 30 is a block diagram showing a configuration of a pulse widthadjusting means of a cold cathode tube driving device in the embodiment5 of the invention. The configurations other than the pulse widthadjusting means are the same as those shown in FIG. 21.

In FIG. 30, numeral 108 b 1 denotes a DFF that latches an initial pulsepzplsa outputted from a DFF 108 b at a leading edge of a clock and thenoutputs the same, numerals 108 d 4 and 108 d 5 are OR gates, numeral 108e 4 denotes a selector that outputs an output signal of the OR gate 108d 4 when Vduty[0] is 1, while outputs the initial pulse pzplsa when itis 0, numeral 108 d 5 denotes a selector that outputs an output signalof the OR gate 108 d 5 when Vduty[0] is 1, while outputs an extendedpulse pzplsb when it is 0, and numeral 108 e 6 denotes a selector thatoutputs an output signal of the selector 108 e 5 when a signal(hereinafter referred to as bunadd that will be explained in detaillater) sent from the frequency dividing means 105 is 1, while outputs anoutput signal of the selector 108 e 4 when it is 0.

Upon explaining the operation of this embodiment, a method for enhancingthe resolution by a process in which the frequency dividing ratioutilizes a trailing edge of a clock will briefly be explained, since itis important.

FIG. 50 shows a configuration of a system for enhancing a frequencyresolution of a driving pulse by using a trailing edge of a clockdisclosed in the Document 4 (Japanese Unexamined Patent Publication No.2000-139081). Numeral 105 a denotes a distributing means that inputslow-order N-bit data among the frequency data Fnext outputted from thefrequency dividing means 105 a and outputs 1 the times applied atFnext[N−1:0] during cycle of nth root of 2 of a driving pulse. Thetiming that the distributing means 105 d outputs 1 is determined by aseparately established distribution technique, that is not especiallyexplained since it is out of the purpose of the invention.

Numeral 105 b denotes an adder that adds Fnext[M-1:N] to the outputsignal from the distributing means 105 d and outputs the resultant.Since the output from the distributing means 105 d is either 1 or 0, alloutputs from the adder 105 b are only Fnext[M-1:N] or Fnext[M-1:N]+1.Numeral 105 c denotes a frequency dividing means that divides a clockonly by a value shown by the output signal from the adder 105 b. Thesecomponents 104 a, 105 b and 105 c constitute the frequency dividingmeans 105.

Numeral 108 a is the pulse width adjusting means (pulse width decodingmeans) explained in the embodiments shown in FIGS. 25 and 28. Althoughthe pulse width adjusting means 108 a is included in the frequencydividing means 105 c in the Document 4, it is separated from thefrequency dividing means for the sake of the convenience. Numeral 108 hdenotes a reverse-edge processing means that latches the output signalfrom the pulse width shaping means 108 a at the trailing edge of theclock and outputs the resultant. Although the Document 4 refers thetrailing edge of a clock as a reverse edge, the meanings of them are thesame. The specific configuration of the reverse-edge processing means108 h is the same as that of the DFF 108 c in FIG. 25. Numeral 108 e 7denotes a selector that outputs an output signal from the reverse-edgeprocessing means 108 h when the value of the distributing means 105 d is1, while outputs an output signal from the pulse width shaping means 108a when it is 0. The output signal from the selector 108 e 7 becomes adriving pulse pzdrv. In this configuration, the output signal from thedistributing means 105 d is the distribution signal bunadd in theembodiment shown in FIG. 30.

FIG. 51 shows a timing waveform chart briefly showing the operation forenhancing the resolution in the dividing ratio by the clock reverse-edgeprocessing shown in the Document 4. FIG. 51 shows a state where thefrequency data Fnext[M-1:N] (shown in (B)) outputted from the frequencysetting means 104 is added to the output value (shown in (C)) from thedistributing means 105 d in which the added value becomes the frequencydividing ratio (shown in (D)), and a pulse is outputted from thefrequency dividing means 105 c (shown in (D)).

The frequency of the driving pulse adjusted to have a suitable pulsewidth by the pulse width shaping means 108 a has a resolution every onecycle of a clock such as 10 cycles, 11 cycles, 10 cycles, 11 cycles, . .. shown in (F).

The driving pulse is delayed by 0.5 cycles by the reverse-edgeprocessing means 108 h and the selector 108 e 7 at the time when thedistribution signal bunadd that is the output from the distributingmeans 105 d is 1, whereby this driving pulse is converted into a drivingpulse having a resolution of every 0.5 cycles shown in (H). The point ofthis technique is that, only by delaying the driving pulse by 0.5 cyclesin synchronization with the distributing means 105 d when the outputfrom the distributing means 105 d is 1, this driving pulse can beconverted into a driving pulse having a resolution of 0.5-cycle steps.

Subsequently explained is a method for combining this technique with themethod for enhancing the pulse width resolution using a trailing edge ofa clock shown in the above-mentioned embodiment.

Prepared at first are, as shown in FIG. 31, a pulse (shown in (C))having a pulse width obtained by extending by 0.5 cycles of a clock thepulse width of the driving pulse having a pulse width W and pulse widthW+1 (this pulse is outputted from the pulse width shaping means 108 aand shown in FIG. 31(B)), and pulses obtained by delaying these twopulses respectively by 0.5 cycles (shown in (D) and (E)).

When the Vduty[0] shown in FIG. 30 is 1, the pulse having the pulsewidth extended by 0.5 cycles is selected. In other words, the pulseshown in (C) or (E) is selected. When the Vduty[0] is 0, the pulse shownin (B) or (D) is contrarily selected. This logic is as stated in theembodiment shown in FIG. 25.

When the distribution signal bunadd that is the output from thedistributing means 105 d is 1, the driving pulse delayed by 0.5 cyclesis selected. In other words, the pulse shown in (D) or (E) is selected.When the bunadd signal is 0, the pulse shown in (B) or (C) is contrarilyselected. The above-mentioned logic is arranged as follows.

(1) When Vduty=0 and bunadd=0, the output from the pulse width shapingmeans 108 a is outputted as it is (see FIG. 31(B)).

(2) When Vduty=0 and bunadd=1, the output from the pulse width shapingmeans 108 a is outputted by delaying by 0.5 cycles (see FIG. 31(D)).

(3) When Vduty=1 and bunadd=0, the output from the pulse width shapingmeans 108 a is outputted by extending by 0.5 cycles (see FIG. 31(C)).

(4) When Vduty=1 and bunadd=1, the output from the pulse width shapingmeans 108 a is outputted by extending by 0.5 cycles as well as bydelaying by 0.5 cycles (see FIG. 31(E)).

The pulse width adjusting means shown in FIG. 30 is configured on thislogic. Specifically, the initial pulse pzplsa outputted from the DFF 108b corresponds to the pulse shown in FIG. 31(B), the extended pulsepzplsc outputted from the OR gate 108 d 4 corresponds to the pulse shownin FIG. 31(C), the delayed pulse pzplsb outputted from the DFF 108 ccorresponds to the pulse shown in FIG. 31(D) and the delayed andextended pulse pzplse outputted from the OR gate 108 d 5 corresponds tothe pulse shown in FIG. 31(E). The selectors 108 e 4 to 108 e 6 are forperforming a change-over and output on the above-mentioned logic.

By this configuration, the driving pulse shown in FIG. 31(H) can beobtained, to thereby be capable of achieving both an enhancement in apulse width resolution by utilizing a trailing edge of a clock and anenhancement in a frequency resolution of a driving pulse.

As explained above, even in case where the frequency dividing ratio ofthe driving pulse has already aimed to enhance the precision by usingthe trailing edge of a clock, the cold cathode tube driving device ofthis embodiment can finely adjust the pulse width of the driving pulseby effectively using the trailing edge of a clock without hindering theeffect of this case, to thereby obtaining an optimum pulse width inaccordance with a power supply voltage. This configuration can bring ahighly efficient driving (reduced power consumption). Further, thistechnique is not deviated from a designing rule of a digital LSI, sothat there is no special problem occurring on making the device as anLSI. Therefore, the device of the invention can be provided as a cheapdigital LSI.

Embodiment 6

A cold cathode tube driving device according to an embodiment 6 of theinvention will be explained below. This embodiment provides a systemcapable of further enhancing a resolution in pulse width control. Theadjustment in pulse width of a driving pulse is desirably performed witha resolution set as small as possible. More preferably, a desirableresolution is the one with which the adjustment can be performed in aminimum of 0.1-V steps of a power supply voltage. As already explainedin the subjects taking specific examples, obtaining a resolution inabout 0.1-V steps within 5 V to 10 V of the power supply voltagerequires a resolution of 50 in this range. If the duty is intended to bechanged by 20 to 30% in this range, the duty has to be changed in 0.2-%steps.

If the sensitivity to the efficiency to the duty value is less so as tobe neglected, a small resolution is naturally all right. The resolutionin the embodiment shown in FIG. 25 is in 0.5-% steps of duty (resolutionin the case of producing a driving pulse by 100-dividing), while theresolution of the configuration utilizing a delay element shown in FIG.28 is in 0.25-% steps. There may be a case that such resolution isinsufficient. The resolution enhances when the delay amount of the delayelement is set not to 1/4 cycles but to less cycle in FIG. 28, but thereis a limit considering the non-uniform delay amount due to a temperaturecharacteristic or power supply voltage.

In view of this, the present embodiment provides a method that adopts afrequency distribution method disclosed in the Document 1 (JapaneseUnexamined Patent Publication No. 2000-133485) for enhancing aresolution by increasing a dummy resolution of a duty ratio bydistributing a duty ratio as shown in FIG. 32. It is to be noted that,since the frequency dividing ratio of a driving pulse is alreadydistributed in a digital system, a uniform waveform cannot be obtainedby simply distributing the duty ratio, to thereby not obtaining asufficient efficiency. The point of this embodiment is that, even incase where a frequency dividing ratio of a driving pulse is alreadydistributed, a distribution of a pulse width is effectively incorporatedtherein.

The method of the embodiment will be explained below. FIG. 33 is a blockdiagram showing a configuration of a cold cathode tube driving deviceaccording to an embodiment 6 of the invention.

In FIG. 33, numeral 109 denotes a pulse width distributing/calculatingmeans that inputs Vduty[n-1:0] that is low-order n-bit of the Vdutyoutputted from the pulse width calculating means 107 and Fnext[n-1:0]that is low-order n-bit of the Fnext outputted from the frequencysetting means 104 and outputs 1 the times applied by Vduty[n-1:0] at nthroot of 2 of a driving pulse.

For example, in case n=4 and Vduty[n-1:0]=1, it outputs 1 only onceduring 16 cycles of a driving pulse. In this case, there are 16positions to which 1 is outputted (in case where 1 is outputted at thefirst cycle to in case where 1 is outputted at 16th cycle). The outputposition is an important point of the present invention, so that it willbe explained in detail below. The value of n is a distribution number ofa driving pulse.

Numeral 110 denotes an adder that adds the value of Vduty[A-1:n] of theA-bit output Vduty outputted from the pulse width calculating means 107to the output value from the pulse width distributing/calculating means109 and outputs the added value to the pulse width adjusting means 108.The output value from the adder 110 is pulse width data. The pulse widthdistributing/calculating means 109 and the adder 110 constitute thepulse width distributing means 111. The other configurations andoperations are the same as those in the embodiment 4 shown in FIG. 21.It is to be noted here that, for simplifying the explanation, the pulsewidth adjusting means 108 is simply configured by the pulse widthshaping means 108 a so that the attempt to enhance a resolution by usinga trailing edge of a clock is not performed. Specifically, the outputvalue from the adder 110 becomes a pulse width as it is. In the presentembodiment, the device is configured such that the output from thedistributing means 105 d (corresponding to a dividing ratio distributingmeans in claims) of the frequency dividing means 105 at (P₀·2⁰+P₁·2¹+ .. . +P_(n-1)·2^(n−1) (wherein P_(X) is a numerical value of 0 or 1))thcycle becomes P₀·Q_(n-1)+_P₀·P₁·Q_(n-2)+ . . . +_P₀·P₁ . . ._P_(n-2)·P_(n-1)·Q₀ (wherein _P_(X) denotes the inversion of P_(X)) fromthe low-order n-bit data (Q₀·2⁰+Q₁·2¹+ . . . +Q_(n-1)·2^(n−1) (whereinQ_(X) is a numerical value of 0 or 1)) among M-bit data outputted fromthe frequency setting means 104 during nth root of 2 of a driving pulseof a piezoelectric transformer. A formula representing this distributionis defined as formula 1.

The specific configuration of the pulse width distributing/calculatingmeans 109 that is the point of the invention is shown in FIG. 34. FIG.34 shows a block diagram in case where n is 4. In FIG. 34, numeral 109 adenotes a comparing means that compares low-order n-bit data (referredto as Fnext[3:0] since n=4) of the data Fnext outputted from thefrequency setting means 104 with low-order n-bit data (referred to asVduty[3:0] since n=4) of the data Vduty outputted from the pulse widthcalculating means 107 and outputs 1 when Fnext[3:0]≧Vduty[3:0]. Numerals109 b 1 to 109 b 8 denote AND gates each having a negative logic input.Numeral 109 c denotes a counter means that counts a number of drivingpulses outputted from the frequency dividing means 105. This countermeans is configured to count from 0 to 2^(n)−1. Since n=4, it is a 4-bitcounter for repeatedly counting from 0 to 15. The output from the 4-bitcounter is represented by Count here, and sth bit signal of the Count isrepresented by Count [s]. Numeral 109 d 0 denotes a selector thatselects the output from the AND gate 109 b 1 when the output from thecomparing means 109 a is 1, while selects the output from the AND gate109 b 2 when the output from the comparing means 109 a is 0. Numerals109 d 1 to 109 d 3 denote selectors performing similar operations.Numeral 109 e 0 denotes an inverter for inverting the Count[0]. Numerals109 e 1 to 109 e 3 are inverters performing the same operations. Numeral109 f 0 denotes a selector that selects the output from the inverter 109e 0 when the output from the selector 109 d 0 is 1 while selects theCount[0] when 0. Numerals 109 f 1 to 109 f 3 are selectors performingthe same operations. Numeral 109 g 1 to 109 g 3 denote AND gates eachhaving negative logical input, numerals 109 h 0 to 109 h 3 denote ANDgates and 109 e OR gate.

The circuit operation shown in FIG. 34 is illustrated as follows. Whenthe output from the dividing ratio distributing means is represented bythe formula 1, this circuit is configured such that the output from thepulse width distributing/calculating means 109 at (P₀·2⁰+P₁·2¹+ . . .+P_(n-1)·2^(n−1) (wherein P_(X) is a numerical value of 0 or 1))th cyclebecomes S₀·R_(n-1)+_S₀·S₁·R_(n-2)+ . . . +_S₀·S₁ . . ._S_(n-2)·S_(n-1)·R₀ (wherein _S_(X) denotes the inversion of S_(X), inwhich S_(X)=(Q_(n-1-X)·_R_(n-1-X))·_P_(X)+_Q(Q_(n-1-X)·_R_(n-1-X))·P_(X)when low-order n-bit data among the M-bit data of the frequency dividingratio is greater than low-order n-bit data of the A-bit pulse widthinformation, whileS_(X)=(_Q_(n-1-X)·R_(n-1-X))·_P_(X)+_(_Q_(n-1-X)·R_(n-1-X))·P_(X) whenthe low-order n-bit data among the M-bit data of the frequency dividingratio is smaller than low-order n-bit data of the A-bit Vduty) from thelow-order n-bit data (R₀·2⁰+R₁2¹+ . . . +R_(n-1)·2^(n−1) (wherein R_(X)is a numerical value of 0 or 1)) of the A-bit output Vduty.

Before explaining the circuit operation shown in FIG. 34, the basic ideaof the present invention will be explained, and then, the explanation ismade the way the circuit shown in FIG. 34 functions in order to realizethis idea. FIG. 35 shows a waveform of a driving pulse for explainingthe point of the invention.

FIG. 35(B) shows an example of the driving pulse having a distributedfrequency dividing ratio. The frequency dividing ratio of the firstdriving cycle is 10, the frequency dividing ratio of the second drivingcycle is 11, the frequency dividing ratio of the third driving cycle is10, the frequency dividing ratio of the fourth driving cycle is 11, andthe frequency dividing ratio of the fifth driving cycle is 10. Theaverage frequency dividing ratio of 5 cycles of the driving pulse is10.4. Further, the pulse width in the waveform (B) is not distributedbut fixed to 4 cycles. In this case, the duty value of 4/10 and 4/11 arepresent in each driving cycle. FIG. 35(C) and FIG. 35(D) show examplesof the case where the pulse width in only 2 cycles is extended by 1cycle during 5 cycles of the driving pulse.

The example of (C) illustrates the case where the pulse width isextended by 1 cycle at the first and third driving cycles. In this case,there are duty values of 4/10, 5/10 and 4/11, apparently not showing auniform duty compared to the case of (B).

The example of (D) illustrates the case where the pulse width isextended by 1 cycle at the second and fourth cycles. In this case, theduty values are 5/11 and 4/10, showing a uniform duty compared to thecase of (C).

In case where the pulse width is distributed to obtain a resolution atthe average pulse width, the pulse width may be extended by 1 cycle atthe driving cycle wherein the frequency dividing ratio is made greaterby 1 cycle for preventing the non-uniformity to obtain a duty ratio asuniform as possible. Specifically, the pulse width may be extended atthe second and fourth driving cycles that are 11 cycles in the exampleshown in FIG. 35. It is needless to say that either case can afford aneffect for improving a resolution due to the pulse width distribution,but the distribution in (D) is desirable for obtaining a greater effect.The first point of this embodiment is that the cycle in which the pulsewidth is extended by 1 cycle is selected among the cycles in which thefrequency dividing ratio is made greater by 1 cycle when the pulse widthis distributed.

In case where the frequency dividing ratio of the driving pulse isdistributed based upon the formula 1, the pulse width may not simply bedistributed based upon the same formula, but some idea is required. Thisis the second point of the present invention.

FIG. 36 shows an example of the case where the pulse width isdistributed by the same system (system of the formula 1), wherein n=3(i.e., distributing during 8 cycles of the driving pulse),Fnext[n-1:0]=3 (i.e., the frequency dividing ratio is made great by 1cycle at 3 cycles among 8 cycles of the driving pulse), andVduty[n-1:0]=4 (i.e., the pulse width is extended by 1 cycle at 4 cyclesamong 8 cycles of the driving pulse).

In FIG. 36, (A) to (C) show output waveforms of the counters (not shown)counting the cycle of the driving pulse, wherein (A) corresponds to P₀in the formula 1, (B) corresponds to P₁ and (C) corresponds to P₂. (D)to (F) in FIG. 36 show each coefficient of Q_(X) in the formula 1.

FIG. 36(G) shows the output (solution obtained from the formula 1) fromthe distributing means 105 d. In case where Fnext[n-1:0]=3 (that is 011in binary notation so that Q₂=0, Q₁=1 and Q₀₌₁ in the formula 1), thelogical sum of (E) and (F) is shown in (G). Further, in case where thedistribution of the pulse width is performed with the same logic, thepulse width is distributed as shown in FIG. 36(H) when Vduty[n-1:0]=4(Q₂=1, Q₁=0 and Q₀=0). In this way, even if both distribution logics arethe same, the cycle wherein the pulse width is extended by 1 cycle bythe distribution of the pulse width is not always selected priorly fromthe cycles where the frequency dividing ratio is made great by 1 cycle.

The present invention avoids this problem by the following technique.This technique is firstly explained in the case whereFnext[n-1:0]≧Vduty[n-1:0]. Considering the case where n=4, Fnext[3:0]=11(1011 in binary notation) and Vduty[3:0]=5 (0101 in binary notation).FIGS. 37(A) to 37 (D) show waveforms of the counters counting the cycleof the driving pulse like those shown in FIGS. 36(A) to 36(C). Thecycles where the frequency dividing ratio is made greater by 1 cycle areshown by · marks in (E) to (H), when Fnext[3:0]=11. Since the value ofVduty[3:0] is 5 (0101), the pulse width is extended by 1 cycle at thepositions marked by Δ in FIGS. 37(E) to 37(F) when the distribution isthe same as the distribution of the frequency dividing ratio. On theother hand, if the value of P₀ is inverted as shown in FIGS. 37(I) to37(L), the pulse width is extended by 1 cycle at the positions marked byΔ in FIGS. 37(I) to 37(L), that match to the distribution positions ofthe frequency dividing ratio (the positions where the frequency dividingratio is made greater by 1 cycle is referred to as the distributionposition below). This is apparent since the distribution is alwaysexecuted at P₀=0 of the waveform shown in FIG. 37(A) in case whereVduty[3:0] is 7 or below. In this case, P₀ may be inverted. On the otherhand, the value of P₁ is inverted when Fnext[3:0]=14 (1110) andVduty[3:0]=10 (1010), for example. Specifically, since the mostsignificant bit of Fnext [3:0] and the most significant bit ofVduty[3:0] are both 1, the distribution positions match with each otherwith respect to this means. The remaining each bit is compared with eachother, i.e., Fnext[2:0] (=110) is compared with Vduty[2:0] (=010). Inthis case, the distribution is executed at P₁=0 of the waveform shown inFIG. 37(B) like the above-mentioned case. Further, the distributionposition at Fnext[2:0] includes the position at P₁=1 since Fnext[2]=1,whereby the distribution position of the pulse width is certainlyselected from the distribution position of the dividing ratio byinverting the value of P₁ in the distribution at Vduty[2:0].

As described above, in case where Fnext[n-1:0]≧Vduty[n-1:0],Fnext[n-1:0] is compared with Vduty[n-1:0] for searching Xmax that isthe maximum value of x satisfying Fnext[x]=1, and the values at(n-1-Xmax)th bit of the distribution cycle counters (corresponding tothose shown in FIGS. 37(A) to 37(D)) are inverted to be applied to theformula 1, resulting in that the distribution positions of the pulsewidth are certainly selected from the distribution positions of thefrequency dividing ratio. Although only the signals at (n-1-Xmax) th bitof the counters may be inverted, all the bits of the counterscorresponding to all x satisfying Fnext[x]=1 may be inverted. This isbecause inverting the signals at (n-1-Xmax)th bit includes all thedistribution positions corresponding to the signals at the followingbits. Further, the circuit is simply configured by inverting each bit ofthe counters corresponding to all x. This is because the circuit forsearching the maximum value of x is unnecessary. Therefore, the circuitshown in FIG. 34 is configured to invert bits corresponding to all x.

The following formula is obtained in case where the values at(n-1-Xmax)th bit of the distribution counters (corresponding to thoseshown in FIGS. 37(A) to 37(C)) are inverted.

The output on the (P₀·2⁰+P₁·2¹+ . . . +P_(n-1)·2^(n−1))th cycle (whereinP_(X) is a numerical value of 0 or 1) becomes S₀·R_(n-1)+_S₀·S₁·R_(n-2)+. . . +_S₀·S₁ . . . _S_(n-2)·S_(n-1)·R₀ (wherein _S_(X) denotes theinversion of S_(X) in which S_(X)=_P_(X) with respect to only themaximum value of n-1-X satisfying Q_(n-1-X)·_R_(n-1-X)1 and S_(X)=P_(X)with respect to the others when low-order n-bit data among the M-bitdata of the frequency dividing ratio is greater than low-order n-bitdata of the A-bit pulse width information, while S_(X)=_P_(X) withrespect to only the maximum value of n−1-X satisfyingQ_(n-1-X)·_R_(n-1-X)=1 and S_(X)=P_(X) with respect to the others whenthe low-order n-bit data among the M-bit data of the frequency dividingratio is smaller than low-order n-bit data of the A-bit Vduty) from thelow-order n-bit data (R₀·2⁰+R₁·2¹+ . . . +R_(n-1)·2^(n−1) (wherein R_(X)is a numeric value of 0 or 1) of the A-bit output Vduty.

The explanation so far is made concerning the case whereFnext[n-1:0]≧Vduty[n-1:0]. The way this system operates in the circuitshown in FIG. 35 will firstly be explained before explaining the systemwhen Fnext[n-1:0]<Vduty[n-1:0].

The comparing means 109 a compares Fnext[n-1:0] with Vduty[n-1:0] andoutputs 1 when Fnext[n-1:0]≧Vduty[n-1:0]. In this case, the output fromthe comparing means 109 a is 1 since Fnext[n-1:0]≧Vduty[n-1:0].Therefore, outputs from AND gates 109 b 1, 109 b 3, 109 b 5 and 109 b 7are selected at the selectors 109 d 0 to 109 d 3. These AND gatesoutputs 1 when Fnext[x]=1 and Vduty[x]=0, while outputs 0 when Fnest[x]is not 1 and Vduty[x] is not 0. In other words, these AND gates search xsatisfying Fnext[x]=1 and Vduty[x]=0.

The counter 109 c is a driving cycle counter. Whether each bit of thiscounter is inverted or not is performed by the inverters 109 e 0 to 109e 3 and selectors 109 f 0 to 109 f 3. If Fnext[2]=1 and Vduty[2]=0, thesignal sell in FIG. 34 becomes 1, so that the Count[1] at the first bitof the counter means 109 c is inverted.

The AND gates 109 g 1 to 109 g 3 serve to making signals of (I) to (L)in FIG. 37. Further, the AND gates 109 h 0 to 109 h 3 and OR gate 109 iselect the meanss marked with Δ in the waveforms (I) to (L) in theexample shown in FIG. 37. By this operation, the distribution positionof the pulse width is certainly selected from the distribution positionof the frequency dividing ratio.

Subsequently explained is the case where Fnext[n-1:0]<Vduty[n-1:0]. Thelogic in this case is contrary. Specifically, the distribution positionof the pulse width is certainly selected from the distribution positionof the frequency dividing ratio when Fnext[n-1:0]≧Vduty[n-1:0]. On theother hand, the distribution position of the frequency dividing ratiomay certainly be selected from the distribution position of the pulsewidth when Fnext[n-1:0]<Vduty[n-1:0]. This can be achieved only bysearching the value of x satisfying Vduty[x]=1 and Fnext[x]=0 contraryto the above-mentioned case where the value of x satisfying Vduty[x]=0and Fnext[x]=1 is searched. This operation can be realized by the ANDgates 109 b 2, 109 b 4, 109 b 6 and 109 b 8 in the circuit shown in FIG.34.

FIG. 38 is a block diagram simply showing the circuit of FIG. 34. InFIG. 38, numeral 109 b_1 denotes a first searching means for searching xsatisfying Fnext[x]=1 and Vduty[x]=0, 109b_2 denotes a second searchingmeans for searching x satisfying Fnext[x]=0 and Vduty[x]=1, and 109 ddenotes a selector that performs a change-over between the searchresults of the first searching means 109 b_1 and the second searchingmeans 109 b_2 from the result of the comparison from the comparing means109 a. The selector 109 d outputs the search result from the firstsearching means 109 b_1 when Fnext[x]≧Vduty[x], while outputs the searchresult from the second searching means 109 b_2 when Fnext[x]<Vduty[x].The first searching means 109 b_1 corresponds to the AND gates 109 b 1,109 b 3, 109 b 5 and 109 b 7 in FIG. 34, while the second searchingmeans 109 b_2 corresponds to the AND gates 109 b 2, 109 b 4, 109 b 6 and109 b 8 in FIG. 34. The selector 109 d corresponds to the selectors 109d 0 to 109 d 3 in FIG. 34. Numeral 109 f in FIG. 38 denotes an invertingmeans for inverting a predetermined bit of the counter means 109 c fromthe search result outputted from the selector 109 d. Specifically, theinverting means inverts the output from the counter means 109 c withrespect to the bit satisfying the search condition of the firstsearching means 109 b_1 or the second searching means 109 b_2. Thisinverting means 109 f corresponds to the inverters 109 e 0 to 109 e 3and selectors 109 f 0 to 109 f 3 in FIG. 34. Numeral 109 g denotes acoefficient calculation means that outputs the final pulse widthdistribution signal from the output of the inverting means 109 f andcorresponds to the AND gates 109 g 1 to 109 g 3, 109 h 0 to 109 h 3 and109 i.

FIG. 39 is a block diagram showing the case where Fnext [x] is comparedwith Vduty[x] for searching the maximum value xmax satisfying Vduty[x]=0and Fnext[x]=1, and only the value at (n-1-xmax)th bit of the countermeans 109 c is inverted. In FIG. 39, numeral 109 j denotes a thirdsearching means that outputs the maximum value xmax among the searchedvalue x based upon the search result outputted from the selector 109 d.The other configurations and operations are the same as those in theblock diagram shown in FIG. 38, so that the effect is also the same.

As described above, the present embodiment provides a system wherein apulse width is distributed to obtain a resolution of a pulse duty at anaverage pulse width among driving pulses during a predetermined cycle.Therefore, the pulse width resolution can remarkably be enhancedcompared to the systems shown in FIGS. 25, 28 and 30. Accordingly, thissystem enables to perform a smooth duty control with respect to a powersupply voltage, thereby improving a driving efficiency of thepiezoelectric transformer. This greatly contributes to power reductionat a backlight means.

Further, the distribution form is approximately uniform in this system,thereby obtaining an effect that the disadvantage (e.g., brightnessflicker) caused by concentrating the distribution positions on aspecific position can almost be neglected.

Although a synchronization with the systems shown in FIGS. 25, 28 and 30is not especially illustrated in the figure, this system can be usedtogether with the Systems in the embodiments 4 and 5 for enhancing theresolution by using a trailing edge of a clock, since the pulse widthinformation (signal outputted from the adder 110 in FIG. 33) obtained inthe embodiment 6 and having the distributed pulse width has a meaningsame as the output signal from the pulse width calculating means 107,for example, shown in FIG. 21 in the embodiment 4.

Each element of the averaging means 102, error voltage calculating means103, frequency setting means 104, frequency dividing means 105, pulsewidth calculating means 107, pulse width adjusting means 108, pulsewidth distributing/calculating means 109, pulse width distributing means111, comparing means 109 a, first searching means 109 b_1, secondsearching means 109 b_2, third searching means 109 b_3, counter means109 c, inverting means 109 f and coefficient calculation means 109 g maybe achieved by a hardware or software or by a hybrid structure incombination with a hardware and software.

INDUSTRIAL APPLICABILITY

As explained in detail, according to the first means to solve thesubjects, the control cycle is set to a cycle A times (A: naturalinteger) the driving pulse N cycle (distribution cycle) for driving Atimes at the same average frequency, and the sampling number N at theaveraging means 102 becomes equal to the sampling number during thedistribution cycle. Therefore, the burst dimming can be realized in thedigital driving system using the frequency distribution of the drivingpulse. Consequently, the present invention can provide a cold cathodetube driving device using a digital system that is advantageous inreducing cost and saving space because of one-chip formation with theother LSIs, to thereby bring a great effect to a further miniaturizationof a small-sized imaging equipment.

Further, according to the second means to solve the subjects, changingthe distribution number in accordance with the burst pulse width enablesto lower the dimming level, thereby being capable of enlarging thedimming range.

Moreover, according to the third means to solve the subjects, thecontinuous driving is executed at the starting, thereby being capable ofshifting to the burst dimming without deteriorating the lightingperformance even in the burst dimming. Further, changing the controlcycle at the starting and at the lighting, or changing the distributionnumber can improve the brightness change at the lighting to a levelalmost neglected, thereby giving an effect of remarkably improving thelighting quality.

Additionally, the fourth means to solve the subjects can provide a pulsewidth resolution with a double precision by using a trailing edge of aclock without deviating from a designing technique of a digital LSI,whereby a driving pulse having an optimum pulse width can be obtainedwithin a wide range of a power supply voltage even in a digital drivingsystem. This leads to reduce power consumption due to an improvement inefficiency and to prevent a break-down of a FET or piezoelectrictransformer because of a surge upon driving the piezoelectrictransformer, thereby bringing a great effect.

Further, according to the fifth means to solve the subjects, even incase where the frequency dividing ratio of the driving pulse has alreadyaimed to enhance the precision by using the trailing edge of a clock,the cold cathode tube driving device of this embodiment can finelyadjust the pulse width of the driving pulse by effectively using thetrailing edge of a clock without hindering the effect of this case, tothereby obtaining an optimum pulse width in accordance with a powersupply voltage. The other effects such as an effect of reduced powerconsumption due to an improvement in efficiency and an effect forpreventing a break-down due to a surge can be obtained similar to thefourth means.

Moreover, the sixth means to solve the subjects provides a systemwherein a pulse width is distributed to obtain a resolution of a pulseduty at an average pulse width among driving pulses during apredetermined cycle. Therefore, the pulse width resolution canremarkably be enhanced compared to the systems shown in FIGS. 25, 28 and30. Accordingly, this system enables to perform a smooth duty controlwith respect to a power supply voltage, thereby improving a drivingefficiency of the piezoelectric transformer. This greatly contributes topower reduction at a backlight means. Further, this system can beutilized in synchronization with the above-mentioned fourth and fifthmeans, thereby not ruining a conventional effect. Additionally, thissystem can be used together with the fourth and fifth means. It isneedless to say that the combination of these systems effectivelycontributes to further improvement in efficiency.

Additionally, a means to perform a driving control of a backlight candigitally be realized in a liquid crystal display device, whereby aliquid crystal driving means and back light driving means are integrallyformed with an LSI to achieve various effects such as a backlightdimming in synchronization with an image, reduced cost, saved space orthe like.

1. A cold cathode tube driving device comprising: a piezoelectrictransformer which outputs an output voltage varying depending upon afrequency of an input voltage to a cold cathode tube which is a load; adata converting device which detects electric current flowing throughsaid cold cathode tube and converts the detected current amount intodigital data; a smoothing process device which smoothes output data fromsaid data converting device at a predetermined timing; an error voltagecalculating device which compares smoothing data obtained from saidsmoothing process device with reference data and outputs error datacorresponding to its difference; a frequency setting device which sets afrequency of said driving pulse on the basis of said error data; afrequency dividing device which divides a clock of a predeterminedfrequency and generates a driving pulse of an average frequencycorresponding to the frequency data outputted from said frequencysetting device in a distribution cycle which is N cycle period of saiddriving pulse; a controller which controls a control cycle so as toperform the same driving for predetermined number of times A (A≧2) atsaid average frequency; a burst pulse generating device which generatesa pulse having a duty width in accordance with a dimming levelexternally applied thereto and having a frequency outputted from saidcontroller; an output enabling device which turns on or off the outputof the driving pulse from said frequency dividing device in accordancewith the output value from said burst pulse generating device; and apower amplifying device which performs inversion with a switching by thedriving pulse from said output enabling device and then outputs to saidpiezoelectric transformer.
 2. A cold cathode tube driving deviceaccording to claim 1, wherein said smoothing process device isconfigured such that an acquisition range of the data to be smoothed isvariable in a unit of multiple of said distribution cycle in accordancewith the pulse width of the burst pulse generated by said burst pulsegenerating device.
 3. A cold cathode tube driving device according toclaim 1, wherein said smoothing process device is configured to performan averaging process.
 4. A cold cathode tube driving device according toclaim 1, wherein a controlling process device including said smoothingprocess device, said error voltage calculating device, said frequencysetting device, said frequency dividing device, said controller, saidburst pulse generating device and said output enabling device isconfigured by software.
 5. A liquid crystal display device comprising: aliquid crystal panel; a cold cathode tube which is a backlight of saidliquid crystal panel; and the cold cathode tube driving device accordingto claim 1, wherein the piezoelectric transformer in said cold cathodetube driving device is connected to said cold cathode tube.
 6. A coldcathode tube driving device comprising: a piezoelectric transformerwhich outputs an output voltage varying depending upon a frequency of aninput voltage to a cold cathode tube which is a load; a data convertingdevice which detects electric current flowing through said cold cathodetube and converts the detected current amount into digital data; asmoothing process device which smoothes output data from said dataconverting device at a predetermined timing; an error voltagecalculating device which compares smoothing data obtained from saidsmoothing process device which reference data and outputs error datacorresponding to its difference; a frequency setting device which sets afrequency of said driving pulse on the basis of said error data; afrequency dividing device which divides a clock of a predeterminedfrequency and generates a driving pulse of an average frequencycorresponding to the frequency data outputted from said frequencysetting device in a distribution cycle which is N cycle period of saiddriving pulse; a controller which controls a control cycle so as toperform the same driving for a predetermined number of times A×k(A≧2, kis a variable value according to said distribution cycle) at saidaverage frequency; a burst pulse generating device which generates apulse having a duty width in accordance with a dimming level externallyapplied thereto and having a frequency outputted from said controller; adistribution number adjusting device which sets said values of N and kdetermining said distribution cycle in conjunction with the burst pulseoutputted from the burst pulse generating device; an output enablingdevice which turns on or off the output of the driving pulse from saidfrequency dividing device in accordance with the output value from saidburst pulse generating device; and a power amplifying device whichperforms inversion with a switching by the driving pulse from saidoutput enabling device and then outputs to said piezoelectrictransformer.
 7. A cold cathode tube driving device according to claim 6,wherein said smoothing process device is configured such that anacquisition range of the data to the smoothed is variable in a unit ofmultiple of said distribution cycle in accordance with the pulse widthof the burst pulse generated by said burst pulse generating device.
 8. Acold cathode tube driving device according to claim 6, wherein saidsmoothing process device is configured to perform an averaging process.9. A cold cathode tube driving device according to claim 6, wherein saiddistribution number adjusting device is configured to determine saidvalue of k such that the control cycle by said controller is madeconstant regardless of said value of N.
 10. A cold cathode tube drivingdevice according to claim 6, wherein said distribution number adjustingdevice is configured to adjust said value of A of said controller inconjunction with the duty of the burst pulse outputted from said burstpulse generating device.
 11. A cold cathode tube driving deviceaccording to claim 6, wherein a controlling process device includingsaid smoothing process device, said error voltage calculating device,said frequency setting device, said frequency dividing device, saidcontroller, said burst pulse generating device, said distribution numberadjusting device and said output enabling device is configured bysoftware.
 12. A liquid crystal display device comprising: a liquidcrystal panel; a cold cathode tube which is a backlight of said liquidcrystal panel; and the cold cathode tube driving device according toclaim 6, wherein said piezoelectric transformer in said cold cathodetube driving device is connected to said cold cathode tube.
 13. A coldcathode tube driving device comprising: a piezoelectric transformerwhich outputs an output voltage varying depending upon a frequency of aninput voltage to a cold cathode tube which is a load; a data convertingdevice which detects electric current flowing through said cold cathodetube and an input voltage of said cold cathode tube and converts each ofthe detected current amounts into digital data; a lighting detectingdevice which detects a lighting from the output from said dataconverting device; a smoothing process device which smoothes output datafrom said data converting device at a predetermined timing; an errorvoltage calculating device which compares smoothing data obtained fromsaid smoothing process device with reference data and outputs error datacorresponding to its difference; a frequency setting device which sets afrequency of said driving pulse on the basis of said error data; afrequency dividing device which divides a clock of a predeterminedfrequency and generates a driving pulse of an average frequencycorresponding to the frequency data outputted from said frequencysetting device in a distribution cycle which is N cycle period of saiddriving pulse; a controller which controls a control cycle so as toperform the same driving for a predetermined number of times A(A≧2) atthe average frequency; a control cycle switching device which switchessaid number of times A in conjunction with a lighting detection pulseoutputted from said lighting detecting device; a dimming level switchingdevice which switches between an externally applied dimming level and aseparately set dimming level in conjunction with the lighting detectionpulse outputted from said lighting detecting device; a burst pulsegenerating device which generates a pulse having a duty width inaccordance with the output from said dimming level switching device andhaving a frequency outputted from said controller; an output enablingdevice which turns on or off the output of the driving pulse from saidfrequency dividing device in accordance with the output value from saidburst pulse generating device; and a power amplifying device whichperforms inversion with a switching by the driving pulse from saidoutput enabling device and then outputs to said piezoelectrictransformer.
 14. A cold cathode tube driving device according to claim13, wherein the number of times A representing the control cycle set atsaid control cycle switching device is set such that the number of timesat the starting is smaller than that at the lighting.
 15. A cold cathodetube driving device according to claim 13, wherein the distributioncycle of said frequency dividing device is switched in conjunction withthe lighting detection pulse outputted from said lighting detectingdevice and is set such that the distribution number at the starting issmaller than that at the fill lighting.
 16. A cold cathode tube drivingdevice according to claim 13, wherein said dimming level switchingdevice is configured to output a dimming level representing 100%continuous driving when the light ing detection pulse outputted fromsaid lighting detecting device has a value showing a non-lighting state.17. A cold cathode tube driving device according to claim 13, wherein acontrolling process device including said smoothing process device, saiderror voltage calculating device, said frequency setting device, saidfrequency dividing device, said controller, said control cycle switchingdevice, said dimming level switching device, said burst pulse generatingdevice and said output enabling device is configured by software.
 18. Aliquid crystal display device comprising: a liquid crystal panel; a coldcathode tube which is a backlight of said liquid crystal panel; and thecold cathode tube driving device according to claim 13, wherein saidpiezoelectric transformer in said cold cathode tube driving device isconnected to said cold cathode tube.
 19. A cold cathode tube drivingdevice which generates a driving pulse obtained by dividing a clock of apredetermined frequency in accordance with a frequency dividing ratiocorresponding to a difference between an electric amount in a coldcathode tube which is a load of a piezoelectric transformer and areference electric amount and outputs the generated pulse to saidpiezoelectric transformer, comprising: a frequency setting device whichobtains dividing ratio information as to said driving pulse from theinformation of said difference; a frequency dividing device whichgenerates a distribution pulse which is a pulse in a state ofdistributing a frequency dividing ratio on the basis of said dividingratio information; a power supply voltage detecting device which detectsa power supply voltage and outputs power supply voltage information; apulse width calculating device which calculates pulse width informationof said distribution pulse on the basis of said power supply voltageinformation and said dividing ratio information; and a pulse widthadjusting device which generates an extended pulse having a pulse widthobtained by extending said pulse width of said distribution pulse on thebasis of said pulse width information as well as switches between saiddistribution pulse and said extended pulse on the basis of said pulsewidth information and then outputs the resultant to a driving element ofthe piezoelectric transformer.
 20. A cold cathode tube driving deviceaccording to claim 19, wherein said pulse width calculating device isconfigured to output the pulse width information, as to saiddistribution pulse, obtained from said power supply voltage informationfrom said power supply voltage detecting device and said dividing ratioinformation from said frequency setting device as data including decimalmeans corresponding to one cycle or less of a clock; and said pulsewidth adjusting device is configured to include: a pulse width shapingdevice which shapes the pulse width of said distribution pulse outputtedfrom said frequency dividing device into a value corresponding to aninteger means of said pulse width information; at least one pulse widthextending device which converts the output from said pulse width shapingdevice into the extended pulse having an extended pulse width; and aswitching device which switches between the output from said pulse widthextending device and the output from said pulse width shaping device inaccordance with the value of the decimal means of said pulse widthinformation and outputs the resultant.
 21. A cold cathode tube drivingdevice which generates a driving pulse obtained by dividing a clock of apredetermined frequency in accordance with a frequency dividing ratiocorresponding to a difference between an electric amount in a coldcathode tube which is a load of a piezoelectric transformer and areference electric amount and outputs the generated pulse to saidpiezoelectric transformer, comprising: a frequency setting device whichobtains dividing ratio information as to said driving pulse from theinformation of said difference; a frequency dividing device whichgenerates a distribution pulse having a dividing ratio of D+1 for Ltimes (L<N) at a period of K cycles of said driving pulse with respectto the reference dividing ratio D; a power supply voltage detectingdevice which detects a power supply voltage; a pulse width calculatingdevice which outputs the pulse width information, as to saiddistribution pulse, obtained from said power supply voltage informationfrom said power supply voltage detecting device and said dividing ratioinformation from said frequency setting device as data including decimalmeans corresponding to one cycle or less of a clock; a pulse widthshaping device which shapes the pulse width of said distribution pulseoutputted from said frequency dividing device into a value correspondingto an integer means of said pulse width information; at least one pulsewidth extending device which converts the output from said pulse widthshaping device into the extended pulse having an extended pulse width;and a switching device which switches between the output from said pulsewidth extending device and the output from said pulse width shapingdevice in accordance with the value of the decimal means of said pulsewidth information and outputs the resultant to a driving element of thepiezoelectric transformer.
 22. A cold cathode lube driving deviceaccording to claim 20 or 21, wherein said pulse width extending devicehas a delay fine-adjusting device which converts the output from saidpulse width shaping device into an extended pulse having a pulse widthextended with the respective delay difference set shorter than one cycleof said clock.
 23. A cold cathode tube driving device according to claim22, wherein said delay fine-adjusting device is configured by a flip-Sflop which latches at a trailing edge or a clock.
 24. A cold cathodetube driving device which generates a driving pulse obtained by dividinga clock of a predetermined frequency in accordance with a frequencydividing ratio corresponding to a difference between an electric amountin a cold cathode tube which is a load of a piezoelectric transformerand a reference electric amount and outputs the generated pulse to saidpiezoelectric transformer, comprising: a frequency setting device whichobtains dividing ratio information as to said driving pulse from theinformation of said difference; a frequency dividing device whichgenerates a distribution pulse being in a state of distributing afrequency dividing ratio on the basis of said dividing ratioinformation; a power supply voltage detecting device which detects apower supply voltage of an input; a pulse width calculating device whichcalculates pulse width information of said distribution pulse on thebasis of said power supply voltage information and said dividing ratioinformation; and a pulse width adjusting device which generates anextended pulse having a pulse width obtained by extending the pulsewidth of said distribution pulse by 0.5 cycles, generates a delayedpulse and delayed and extended pulse each having a pulse width obtainedby delaying said distribution pulse and said extended pulse by 0.5cycles on the basis of said pulse width information from the pulse widthcalculating device, switches among said distribution pulse, saidextended pulse, said delayed pulse and said delayed and extended pulseon the basis of the pulse width information, and then outputs theresultant to a driving element of the piezoelectric transformer.
 25. Acold cathode lube driving device according to claim 24, wherein saidpulse width calculating device is configured to output the pulse widthinformation of said distribution pulse, obtained from said power supplyvoltage information from said power supply voltage detecting device andsaid dividing ratio information from said frequency setting device asdata including decimal means corresponding to one cycle or less of aclock; and said pulse width adjusting device is configured to include: apulse width shaping device which shapes the pulse width of saiddistribution pulse outputted from said frequency dividing device into avalue corresponding to an integer part of said pulse width information;a 1-clock-cycle delaying device which latches the output from said pulsewidth shaping device at the leading edge of a clock; a 0.5-clock-cycledelaying device which latches the output from said pulse width shapingdevice at the trailing edge of a clock; and a switching device which, tothe driving element of the piezoelectric transformer, outputs the outputfrom said pulse width shaping device when low-order 1-bit value of saidA-bit pulse width information is at low level and said dividing ratio isD, outputs the output from said 0.5-clock-cycle delaying device whenlow-order 1-bit value of said A-bit pulse width information is at lowlevel and said dividing ratio is D+1, outputs a logical sum of theoutput from said 0.5-clock-cycle delaying device and the output fromsaid pulse width adjusting device when low-order 1-bit value of saidA-bit pulse width information is at high level and said dividing ratiois D, and outputs a logical sum of the output from said 0.5-clock-cycledelaying device and the output from said 1-clock-cycle delaying devicewhen low-order 1-bit value of said A-bit pulse width information is athigh level and said dividing ratio is D+1.
 26. A cold cathode tubedriving device which generates a driving pulse obtained by dividing aclock of a predetermined frequency in accordance with a frequencydividing ratio corresponding to a difference between an electric amountin a cold cathode tube which is a load of a piezoelectric transformerand a reference electric amount, and then outputs the generated pulse tosaid piezoelectric transformer, comprising: a frequency setting devicewhich obtains dividing ratio information as to said driving pulse fromthe information of said difference; a frequency dividing device whichproduces a distribution pulse having a dividing ratio of D+1 at L times(L<K) during K cycles of said driving pulse with respect to thereference dividing ratio D; a power supply voltage detecting devicewhich detects a power supply voltage of an input; a pulse widthcalculating device which outputs the pulse width information obtainedfrom said power supply voltage information from said power supplyvoltage detecting device and said dividing ratio information from saidfrequency setting device as data including decimal device correspondingto one cycle or less of a clock; a pulse width shaping device whichshapes the pulse width of said distribution pulse outputted from saidfrequency dividing device into a value corresponding to an integer meansof said pulse width information; a 1-clock-cycle delaying device whichlatches the output from said pulse width shaping device at the leadingedge of a clock; a 0.5-clock-cycle delaying device which latches theoutput from said pulse width shaping device at the trailing edge of aclock; and a switching device which, to the driving element of thepiezoelectric transformer, outputs the output from said pulse widthshaping device when low-order 1-bit value of said A-bit pulse widthinformation is at low level and said dividing ratio is D, outputs theoutput from said 0.5-clock-cycle delaying device when low-order 1-bitvalue of said A-bit pulse width information is at low level and saiddividing ratio is D+1, outputs a logical sum of the output from said0.5-clock-cycle delaying device and the output from said pulse widthadjusting device when low-order 1-bit value of said A-bit pulse widthinformation is at high level and said dividing ratio is D, and outputs alogical sum of the output from said 0.5-clock-cycle delaying device andthe output from said 1-clock-cycle delaying device when low-order 1-bitvalue of said A-bit pulse width information is at high level and saiddividing ratio is D+1.
 27. A cold cathode tube driving device whichgenerates a driving pulse obtained by dividing, a clock of apredetermined frequency in accordance with a frequency dividing ratiocorresponding to a difference between an electric amount in a coldcathode lube which is a load of a piezoelectric transformer and areference electric amount and outputs the generated pulse to saidpiezoelectric transformer, comprising: a frequency setting device whichobtains dividing ratio information as to the driving pulse from theinformation of said difference; a frequency dividing device whichproduces a distribution pulse which is a pulse for distributing afrequency dividing ratio based upon said dividing ratio information; apower supply voltage detecting device which detects a power supplyvoltage of an input: a pulse width calculating device which calculatespulse width information of said distribution pulse based upon the powersupply voltage information and said dividing ratio information; a pulsewidth distributing device which inputs the pulse width information fromsaid pulse width calculating device, increases said pulse widthinformation at a predetermined timing and outputs said increasedinformation; and a pulse width adjusting device which adjusts the pulsewidth of said distribution pulse according to the output from said pulsewidth distributing device and outputs the adjusted pulse width to adriving element of the piezoelectric transformer.
 28. A cold cathodetube driving device according to claim 27, wherein said pulse widthcalculating device is configured to output said pulse width informationas A-bit data based upon said power supply voltage information and thedividing ratio information obtained at said frequency dividing device,and said pulse width distributing device is configured to output dataobtained by adding 1 to the high-order (A-n)-bit data of said A-bitpulse width information during nth root of 2 of the distribution pulsethe times represented by the low-order n-bit of said A-bit pulse widthinformation.
 29. A cold cathode tube driving device which generates adriving pulse obtained by dividing a clock of a predetermined frequencyin accordance with a frequency dividing ratio corresponding to adifference between an electric amount in a cold cathode tube which is aload of a piezoelectric transformer and a reference electric amount andoutputs the generated pulse to said piezoelectric transformer,including: a frequency setting device for obtaining dividing ratioinformation as to said driving pulse from the information of saiddifference; a frequency dividing device which produces a distributionpulse having a dividing ratio of D+1 for L times (L<K) during K cyclesof said driving pulse with respect to the reference dividing ratio D; apower supply voltage detecting device which detects a power supplyvoltage of an input; a pulse width calculating device which outputs saidpulse width information as A-bit data based upon said power supplyvoltage information and the dividing ratio information obtained at saidfrequency dividing device; and a pulse width distributing device whichoutputs data obtained by adding 1 to the high-order (A-n)-bit data ofsaid A-bit pulse width information during nth root of 2 of thedistribution pulse the times represented by the low-order n-bit of saidA-bit pulse width information.
 30. A cold cathode tube driving deviceaccording to any of claims 27 to 29, wherein said pulse widthdistributing device is configured to distribute a distribution pulsesuch that the duty ratio of the pulse width of said distribution pulsebecomes approximately constant, said frequency dividing device isconfigured to include: a frequency dividing device which divides a clockhaving a predetermined frequency with the dividing ratio D representedby high-order (M-n)-bit data of said M-bit dividing ratio information inorder to make the duty ratio of said pulse width of the distributionpulse approximately constant; and a dividing ratio distributing devicewhich outputs 1 during nth root of 2 of said distribution pulse thetimes represented by the low-order n-bit of said M-bit dividing ratioinformation to make said dividing ratio of the frequency dividing deviceD÷1, and said pulse width distributing device is configured to add 1 tothe high-order (A-n)-bit data of said A-bit pulse width information whenthe output from said dividing ratio distributing device is
 1. 31. A coldcathode tube driving device according to any of claims 27 to 29, whereinsaid pulse width distributing device is configured such that, in orderto add 1 to the high-order (A-n)-bit data of said A-bit pulse widthinformation when the output from the dividing ratio distribution data is1, the output on the (P₀·2⁰+P₁·2¹+ . . . +P_(n-1)·2^(n−1))th cycle ofthe distribution pulse becomes (P₀·Q_(n-1)+_P₀·P₁·Q_(n-2)+ . . . +_P₀·P₁. . . _P_(n-2)·P_(n-1)·Q₀) from the low-order a-bit data (Q₀·2⁰+Q₁·2¹+ .. . +Q_(n-1)·2^(n−1)) among the M-bit data outputted from said frequencysetting device, and is configured to include: a comparing device whichcompares the tow-order n-bit data of the dividing ratio distributiondata with the low-order n-bit data of the pulse width information on thecondition which the adding value of the pulse width on the (P₀·2⁰+P₁·2¹+. . . −P_(n-1)·2^(n−1))th cycle of said pulse width distributionsatisfiesS_(X)=(Q_(n-1-X)·_R_(n-1-X))·_P_(X)+_Q(Q_(n-1-X)·_R_(n-1-X))·P_(X) whenlow-order n-bit data among said M-bit data of the frequency dividingratio is greater than low-order n-bit data of said A-bit pulse widthinformation, while satisfiesS_(X)=(_Q_(n-1-X)·R_(n-1-X))·_P_(X)+_(_Q_(n-1-X)·R_(n-1-X))·P_(X) whenthe low-order n-bit data among said M-bit data of the frequency dividingratio is smaller than low-order n-bit data of said A-bit pulse widthinformation, wherein P_(X), Q_(X) and R_(X) are 0 or 1 and _P_(X),_Q_(X) and _R_(X) respectively represent the inversions of P_(X), Q_(X)and R_(X); a first searching device for searching a bit where saidlow-order n-bit of the dividing ratio distribution data is 1 and thelow-order n-hit data of said pulse width information is 0; a secondsearching device for searching a bit when said low-order n-bit of thedividing ratio distribution data is 0 and the low-order n-bit data ofsaid pulse width information is 1; a switching device which outputs theresult from said first searching device when the low-order n-bit of thedividing ratio distribution data is greater than said low-order n-bitdata of the pulse width information in said comparing device, whileoutput the result from said second searching device when smaller; acounter device which counts a period corresponding to a cycle of nthroot of 2 of said driving pulse; and an inverting device which inverts apredetermined bit of said counter device according to the output fromsaid switching device, whereby said value S_(X) is obtained.
 32. A coldcathode tube driving device according to any of claims 27 to 29, whereinsaid pulse width distributing device is configured such that, in orderto add 1 to the high-order (A-n)-bit data of said A-bit pulse widthinformation when the output from said dividing ratio distribution datais 1, the output on the (P₀·2⁰+P₁·2¹+ . . . +P_(n-1)·2^(n−1))th cycle ofthe distribution pulse becomes (P₀·Q_(n-1)+_P₀·P₁·Q_(n-2)+ . . . +_P₀·P₁. . . _P_(n-2)·P_(n-1)·Q₀) from the low-order n-bit data (Q₀·2⁰+Q₁·2¹+ .. . +Q_(n-1)·2^(n−1)) among the M-bit data outputted from said frequencysetting device, and is configured to include: a comparing device whichcompares the low-order n-bit data of said dividing ratio distributiondata with the low-order n-bit data of the pulse width information on thecondition that the adding value of the pulse width on the (P₀·2⁰+P₁·2¹+. . . +P_(n-1)·2^(n−1))th cycle of said pulse width distributing devicesatisfies S_(X)=_P_(X) with respect to only the maximum value of n-1-Xsatisfying Q_(n-1-X)·_R_(n-1-X)=1 and S_(X)=P_(X) with respect to theothers when low-order n-bit data among said M-bit data of the frequencydividing ratio is greater than low-order n-bit data of the A-bit pulsewidth information, while S_(X)=_P_(X) with respect to only the maximumvalue of n-1-X satisfying _Q_(n-1-X)·R_(n-1-X)=1 and S_(X)=_P_(X) withrespect to the others when the low-order n-bit data among said M-bitdata of the frequency dividing ratio is smaller than low-order n-bitdata of said A-bit pulse width information, wherein P_(X), Q_(X) andR_(X) are 0 or 1 and _P_(X), _Q_(X) and _R_(X) respectively representthe inversions of P_(X), Q_(X) and R_(X); a first searching device forsearching a bit where said low-order n-bit of the dividing, ratiodistribution data is 1 and the low-order n-bit data of said pulse widthinformation is 0; a second searching device for searching a bit wheresaid low-order n-bit of the dividing, ratio distribution data is 0 andthe low-order n-bit data of said pulse width information is 1; aswitching device which outputs the result from said first searchingdevice when said low-order n-bit of the dividing ratio distribution datais greater than said low-order n-bit data of the pulse width informationin said comparing device, while outputs the result from said secondsearching device when smaller; a third searching device for searchingthe most significant bit among the search result outputted from saidswitching device; a counter device which counts a period correspondingto a cycle of nth root of 2 of said driving pulse; and an invertingdevice which inverts a predetermined bit of said counter deviceaccording to the output from said third searching device, whereby saidvalue of S_(X) is obtained.
 33. A cold cathode tube driving deviceaccording to any of claims 19-21 or 23-29 further including: in front ofsaid frequency setting device, a current detecting device for detectinga current flowing through said cold cathode tube; a rectifying devicewhich converts a sinusoidal voltage obtained from said current detectingdevice into an approximately DC voltage; an A/D converter which convertssaid rectified voltage signal into a digital signal; a smoothing processdevice for smoothing the output data from said A/D converter; and anerror voltage calculating device which multiplies difference databetween the externally applied reference data and the output data fromsaid smoothing process device by a constant and outputs the resultant tosaid frequency setting device as error data.
 34. A liquid crystaldisplay device comprising: a liquid crystal panel; a cold cathode tubewhich is a back light of said liquid crystal panel; and a cold cathodetube driving device according to any of claims 19-21 or 23-29, whereinsaid piezoelectric transformer in said cold cathode tube driving deviceis connected to said cold cathode tube.